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WT6116 View Datasheet(PDF) - Weltrend Semiconductor

Part Name
Description
Manufacturer
WT6116 Datasheet PDF : 39 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
WT6132/WT6124/WT6116
Data Sheet Rev. 1.01
SYNC Processor
The functional block diagram of Sync Processor is shown in Fig.4. It contains H and V polarity detection
circuit, H and V frequency counter, composite sync signal separation circuit, free-running H and V sync
signal generator, vedio signal generation circuit for burn-in test and clamp pulse generator.
SOG
HIN
MUX
SOGIN
H Period Counter
SEPART
H Polarity
Detect
EXTRHS
Composite Signal
Separator
EXTRVS
HINPOL
MUX
H Freq Counter
MUX
BYPASS
ENFREE
HOPOL
MUX
H Polarity Control
FREEHS
HOUT
FREE2
FREE1
FREE0
Free-running Sync
Signal Generator
VIN
FREEVS
SEPART
ENFREE
MUX
MUX
Clamp Pulse
Generator
VOPOL
V Polarity Control
VINPOL
V Polarity Detect
CLAMP
VOUT
PAT1
PAT0
Test Pattern
Generator
V Freq Counter
PAT
Fig.4 Block diagram of sync signal processor
Horizontal Polarity Detect
The horizontal polarity is detected by sampling HIN signal at 5.5~6.5us after rising and falling edge of
HIN. If the result of sampling is low and lasts 192~256us with no change, the polarity is positive
(HINPOL=1). If the result of sampling is high and lasts 192~256us with no change, the polarity is
negative (HINPOL=0).
Vertical Polarity Detect
Vertical polarity is detected by sampling VIN level at 2.048ms after rising edge of VIN. If the level is low,
the polarity is positive (VINPOL=1). If the level is high, the polarity is negative (VINPOL=0). But if
SEPART bit is set, the VINPOL bit is “1” because the Vsync from composite signal separator is always
positive polarity.
Output Polarity Control
The polarities of HOUT and VOUT are controlled by HOPOL and VOPOL bites. When the bit is set, the
output polarity is positive. When the bit is cleared, the output polarity is negative.
Weltrend Semiconductor, Inc.
Page 9

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