QL4016-0CG84M View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

QL4016-0CG84M

Military QuickRAM

Unspecified 

Military QuickRAM Family Data Sheet

• • • • • • Up to 90,000 Usable PLD Gates QuickRAM Combining

Performance, Density and Embedded RAM

Device Highlights

High Performance & High Density

• Up to 90,000 usable PLD gates with up to

316 I/Os

• 300 MHz 16-bit counters, 400 MHz datapaths,

160+ MHz FIFOs

• 0.35 µm four-layer metal non-volatile CMOS

process

High Speed Embedded SRAM

• Up to 22 dual-port RAM modules, organized in

user-configurable 1,152 bit blocks

• 5 ns access times, each port independently

accessible

• Fast and efficient for FIFO, RAM, and ROM

functions

Easy to Use/Fast Development

Cycles

• 100% routable with 100% utilization and

complete pin-out stability

• Variable-grain logic cells provide high

performance and 100% utilization

• Comprehensive design tools include high quality

Verilog/VHDL synthesis

Advanced I/O Capabilities

• Interfaces with 3.3 V and 5.0 V devices

Up to 316 I/O Pins

• 316 bi-directional input/output pins,

PCI-compliant for 5.0 V and 3.3 V buses for

-1/-2 speed grades

• Eight high-drive input/distributed network pins

Eight Low-Skew Distributed

Networks

• Two array clock/control networks are available to

the logic cell flip-flop; clock, set, and reset inputs

— each can be driven by an input-only pin

• Six global clock/control networks available to the

logic cell; F1, clock, set, and reset inputs and the

data input, I/O register clock, reset, and enable

inputs as well as the output enable control—each

can be driven by an input-only, I/O pin, any logic

cell output, or I/O cell feedback

High Performance Silicon

• Input + logic cell + output total delays under 6 ns

• Data path speeds over 400 MHz

• Counter speeds over 300 MHz

• FIFO speeds over 160+ MHz

Military Reliability

• Mil-STD-883 and Mil Temp Ceramic

• Mil Temp Plastic - Guaranteed -55°C to 125°C

Figure 1: Military QuickRAM Block Diagram

• PCI compliant with 3.3 V and 5.0 V busses for

-1/-2 speed grades

• Full JTAG boundary scan

22

RAM

Blocks

• Registered I/O cells with individually controlled

clocks and output enables

1,584

High Speed

Logic Cells

Interface

© 2007 QuickLogic Corporation

www.quicklogic.com

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