IT8510TE View Datasheet(PDF) - ITE Tech. INC.

Part Name

Description

Manufacturer

IT8510TE

Embedded Controller

ITE Tech. INC. 

Contents

Table 5-26. Pin States of UART Interface......................................................................................................... 26

Table 5-27. Pin States of GPIO Interface.......................................................................................................... 26

Table 5-28. Pin States of ADC Input Interface .................................................................................................. 26

Table 5-29. Pin States of DAC Output Interface ............................................................................................... 27

Table 5-30. Pin States of Clock......................................................................................................................... 27

Table 5-31. Reset Sources................................................................................................................................ 29

Table 5-32. Reset Types and Applied Module .................................................................................................. 29

Table 5-33. Clock Types ................................................................................................................................... 30

Table 5-34. Power Saving by EC Clock Operation Mode ................................................................................. 32

Table 5-35. Module Status in Each Power State/Clock Operation ................................................................... 33

Table 5-36. Pins with Pull Function................................................................................................................... 34

Table 5-37. Pins with Schmitt-Trigger Function ................................................................................................ 35

Table 5-38. Signals with Open-Drain Function ................................................................................................. 35

Table 6-1. LPC/FWH Response........................................................................................................................ 40

Table 6-2. Host View Register Map, PNPCFG ................................................................................................. 44

Table 6-3. Host View Register Map, Logical Devices ....................................................................................... 45

Table 6-4. Host View Register Map via Index-Data I/O Pair, Standard Plug and Play Configuration Registers46

Table 6-5. Interrupt Request (IRQ) Number Assignment, Logical Device IRQ via SERIRQ ............................ 46

Table 6-6. Logical Device Number (LDN) Assignments ................................................................................... 47

Table 6-7. Host View Register Map via Index-Data I/O Pair, SWUC Logical Device ....................................... 53

Table 6-8. Host View Register Map via Index-Data I/O Pair, KBC / Mouse Interface Logical Device.............. 55

Table 6-9. Host View Register Map via Index-Data I/O Pair, KBC / Keyboard Interface Logical Device ......... 56

Table 6-10. Host View Register Map via Index-Data I/O Pair, SMFI Interface Logical Device ........................ 57

Table 6-11. Host View Register Map via Index-Data I/O Pair, RTC Logical Device......................................... 61

Table 6-12. Host View Register Map via Index-Data I/O, PM1 Logical Device ................................................ 63

Table 6-13. Host View Register Map via Index-Data I/O, PM2 Logical Device ................................................ 64

Table 6-14. Mapped Host Memory Address ..................................................................................................... 70

Table 6-15. M-bus Grant Behavior.................................................................................................................... 72

Table 6-16. EC View Register Map, SMFI ........................................................................................................ 76

Table 6-17. Host View Register Map, SMFI...................................................................................................... 83

Table 6-18. Host View Register Map, SWUC ................................................................................................... 90

Table 6-19. EC View Register Map, SWUC...................................................................................................... 93

Table 6-20. Host View Register Map, KBC ....................................................................................................... 99

Table 6-21. EC View Register Map, KBC ....................................................................................................... 101

Table 6-22. Host View Register Map, PMC .................................................................................................... 108

Table 6-23. EC View Register Map, PMC....................................................................................................... 110

Table 6-24. Host View Register Map, RTC ..................................................................................................... 116

Table 6-25. Host View Register Map via Index-Data I/O Pair, RTC Bank 0 ................................................... 118

Table 6-26. Host View Register Map via Index-Data I/O Pair, RTC Bank 1 ................................................... 118

Table 7-1. 8032 Port Usage ........................................................................................................................... 127

Table 7-2. System Interrupt Table................................................................................................................... 129

Table 7-3. Timer 2 Modes of Operation .......................................................................................................... 136

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IT8510E/TE/G V0.7.2

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