IT8510TE View Datasheet(PDF) - ITE Tech. INC.
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Description
Manufacturer
IT8510TE Datasheet PDF : 284 Pages
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Contents
CONTENTS
1. Features ....................................................................................................................................................... 1
2. General Description ....................................................................................................................................... 3
3. System Block Diagram................................................................................................................................... 5
3.1 Block Diagram..................................................................................................................................... 5
3.2 Host/EC Mapped Memory Space ....................................................................................................... 6
3.3 EC Mapped Memory Space................................................................................................................ 9
3.4 Register Abbreviation........................................................................................................................ 10
4. Pin Configuration ......................................................................................................................................... 11
5. Pin Descriptions ........................................................................................................................................... 17
5.1 Pin Descriptions ................................................................................................................................ 17
5.2 Chip Power Planes and Power States .............................................................................................. 23
5.3 Pin Power Planes and States ........................................................................................................... 24
5.4 PWRFAIL# Interrupt to INTC ........................................................................................................... 28
5.5 Reset Sources and Types................................................................................................................. 29
5.5.1 Relative Interrupts to INTC................................................................................................... 29
5.6 Chip Power Mode and Clock Domain ............................................................................................... 30
5.7 Pins with Pull, Schmitt-Trigger or Open-Drain Function ................................................................... 34
5.8 Power Consumption Consideration .................................................................................................. 36
6. Host Domain Functions................................................................................................................................ 39
6.1 Low Pin Count Interface.................................................................................................................... 39
6.1.1 Overview............................................................................................................................... 39
6.1.2 Features ............................................................................................................................... 39
6.1.3 Accepted LPC Cycle Type ................................................................................................... 39
6.1.4 Debug Port Function ............................................................................................................ 40
6.1.5 Serialized IRQ (SERIRQ) ..................................................................................................... 40
6.1.6 Relative Interrupts to INTC/WUC ......................................................................................... 41
6.1.7 LPCPD# and CLKRUN#....................................................................................................... 42
6.1.8 Check Items.......................................................................................................................... 43
6.2 Plug and Play Configuration (PNPCFG) ........................................................................................... 44
6.2.1 Logical Device Assignment .................................................................................................. 47
6.2.2 Super I/O Configuration Registers ....................................................................................... 48
6.2.2.1 Logical Device Number (LDN)................................................................................. 48
6.2.2.2 Chip ID Byte 1 (CHIPID1)........................................................................................ 48
6.2.2.3 Chip ID Byte 2 (CHIPID2)........................................................................................ 48
6.2.2.4 Chip Version (CHIPVER)......................................................................................... 48
6.2.2.5 Super I/O Control Register (SIOCTRL) ................................................................... 48
6.2.2.6 Super I/O IRQ Configuration Register (SIOIRQ)..................................................... 49
6.2.2.7 Super I/O General Purpose Register (SIOGP)........................................................ 49
6.2.2.8 Super I/O Power Mode Register (SIOPWR) ........................................................... 50
6.2.3 Standard Logical Device Configuration Registers................................................................ 50
6.2.3.1 Logical Device Activate Register (LDA)................................................................... 51
6.2.3.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 51
6.2.3.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 51
6.2.3.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 51
6.2.3.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 52
6.2.3.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 52
6.2.3.7 Interrupt Request Type Select (IRQTP) .................................................................. 52
6.2.3.8 DMA Channel Select 0 (DMAS0) ............................................................................ 53
6.2.3.9 DMA Channel Select 0 (DMAS1) ............................................................................ 53
6.2.4 System Wake-Up Control (SWUC) Configuration Registers ............................................... 53
6.2.4.1 Logical Device Activate Register (LDA)................................................................... 53
6.2.4.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 53
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IT8510E/TE/G V0.7.2
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