IT8510TE View Datasheet(PDF) - ITE Tech. INC.
Part Name
Description
Manufacturer
IT8510TE Datasheet PDF : 284 Pages
| |||
Contents
6.2.10.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 65
6.2.10.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 65
6.2.10.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 65
6.2.10.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 65
6.2.10.7 Interrupt Request Type Select (IRQTP) .................................................................. 65
6.2.11 Programming Guide ............................................................................................................. 67
6.3 Shared Memory Flash Interface Bridge (SMFI) ................................................................................ 69
6.3.1 Overview............................................................................................................................... 69
6.3.2 Features ............................................................................................................................... 69
6.3.3 Function Description............................................................................................................. 69
6.3.3.1 Flash Requirement .................................................................................................. 69
6.3.3.2 Host to M Bus Translation ....................................................................................... 69
6.3.3.3 Memory Mapping ..................................................................................................... 69
6.3.3.4 Indirect Memory Read/Write Transaction ................................................................ 70
6.3.3.5 Locking Between Host and EC Domains................................................................. 70
6.3.3.6 Host Access Protection............................................................................................ 71
6.3.3.7 Response to a Forbidden Access............................................................................ 71
6.3.3.8 Scratch SRAM ......................................................................................................... 71
6.3.3.9 No-wait Mode........................................................................................................... 72
6.3.3.10 Flash Interface ......................................................................................................... 72
6.3.4 EC Interface Registers ......................................................................................................... 76
6.3.4.1 FBIU Configuration Register (FBCFG) .................................................................... 76
6.3.4.2 Flash Programming Configuration Register (FPCFG)............................................. 77
6.3.4.3 Memory Zone Configuration Register (MZCFG) ..................................................... 77
6.3.4.4 Static Memory Zone Configuration Register (SMZCFG)......................................... 78
6.3.4.5 Flash EC Code Banking Select Register (FECBSR)............................................... 79
6.3.4.6 Flash Memory Size Select Register (FMSSR) ........................................................ 79
6.3.4.7 Flash Memory Prescaler Register (FMPSR) ........................................................... 80
6.3.4.8 Shared Memory EC Control and Status Register (SMECCS)................................. 80
6.3.4.9 Shared Memory Host Semaphore Register (SMHSR) ............................................ 81
6.3.4.10 Shared Memory EC Override Read Protect Registers 0-9 (SMECORPR 0-9) ....... 81
6.3.4.11 Shared Memory EC Override Write Protect Registers 0-9 (SMECOWPR0-9) ....... 82
6.3.5 Host Interface Registers....................................................................................................... 83
6.3.5.1 Shared Memory Indirect Memory Address Register 0 (SMIMAR0) ........................ 84
6.3.5.2 Shared Memory Indirect Memory Address Register 1 (SMIMAR1) ........................ 84
6.3.5.3 Shared Memory Indirect Memory Address Register 2 (SMIMAR2) ........................ 84
6.3.5.4 Shared Memory Indirect Memory Address Register 3 (SMIMAR3) ........................ 84
6.3.5.5 Shared Memory Indirect Memory Data Register (SMIMDR) ................................... 84
6.3.5.6 Shared Memory Host Access Protect Register 1-4 (SMHAPR1-4)........................ 84
6.3.5.7 Shared Memory Host Semaphore Register (SMHSR) ............................................ 85
6.4 System Wake-Up Control (SWUC) ................................................................................................... 86
6.4.1 Overview............................................................................................................................... 86
6.4.2 Features ............................................................................................................................... 86
6.4.3 Functional Description.......................................................................................................... 86
6.4.3.1 Wake-Up Status....................................................................................................... 86
6.4.3.2 Wake-Up Events...................................................................................................... 87
6.4.3.3 Wake-Up Output Events .......................................................................................... 88
6.4.3.4 Other SWUC Controlled Options............................................................................. 88
6.4.4 Host Interface Registers....................................................................................................... 90
6.4.4.1 Wake-Up Event Status Register (WKSTR) ............................................................. 90
6.4.4.2 Wake-Up Event Enable Register (WKER)............................................................... 91
6.4.4.3 Wake-Up Signals Monitor Register (WKSMR) ........................................................ 91
6.4.4.4 Wake-Up ACPI Status Register (WKACPIR) .......................................................... 92
6.4.4.5 Wake-Up SMI Enable Register (WKSMIER) ........................................................... 92
6.4.4.6 Wake-Up IRQ Enable Register (WKIRQER) ........................................................... 93
6.4.5 EC Interface Registers ......................................................................................................... 93
www.ite.com.tw
iii
IT8510E/TE/G V0.7.2
Share Link: 