RL56CSM-3 View Datasheet(PDF) - Conexant Systems

Part Name

Description

Manufacturer

RL56CSM-3

AnyPort™ Multi-Service Access Processor

Conexant Systems 

RL56CSMV/3 and RL56CSM/3 Hardware Interface Description

Table of Contents

1137

1. INTRODUCTION................................................................................................................................................. 1-1

1.1 SUMMARY ............................................................................................................................................... 1-1

1.2 FEATURES .............................................................................................................................................. 1-2

1.3 TECHNICAL OVERVIEW......................................................................................................................... 1-3

1.3.1 General Description ..................................................................................................................... 1-3

1.3.2 Digital Data Pump (DDP) ............................................................................................................. 1-3

1.3.3 ARM Microcontroller (MCU)......................................................................................................... 1-3

1.3.4 Access Processor Operation ....................................................................................................... 1-3

1.3.5 Access Processor Firmware ........................................................................................................ 1-3

1.3.6 Supported Interfaces ................................................................................................................... 1-5

2. TECHNICAL SPECIFICATIONS ........................................................................................................................ 2-1

2.1 ESTABLISHING DATA MODEM CONNECTIONS................................................................................... 2-1

2.2 DATA MODE ............................................................................................................................................ 2-1

2.3 ERROR CORRECTION AND DATA COMPRESSION............................................................................. 2-2

2.4 FAX OPERATION .................................................................................................................................... 2-2

2.5 DIAGNOSTICS......................................................................................................................................... 2-2

2.5.1 Commanded Tests....................................................................................................................... 2-2

2.5.2 DDP Test ..................................................................................................................................... 2-3

2.6 LOW POWER SLEEP MODE................................................................................................................... 2-3

3. HARDWARE INTERFACE ................................................................................................................................. 3-1

3.1 HARDWARE SIGNALS ............................................................................................................................ 3-1

3.2 ELECTRICAL AND ENVIRONMENTAL SPECIFICATIONS .................................................................. 3-15

3.2.1 Operating Conditions and Absolute Maximum Ratings ............................................................. 3-15

3.2.2 Current and Power Requirements ............................................................................................. 3-15

3.2.3 Thermal Characteristics ............................................................................................................. 3-17

3.3 INTERFACE TIMING AND WAVEFORMS............................................................................................. 3-19

3.3.1 External SDRAM........................................................................................................................ 3-19

3.3.2 T1/E1 Transceiver Interface Timing........................................................................................... 3-20

3.3.3 Oscillator Waveform Requirements ........................................................................................... 3-21

3.4 SDRAM INTERFACE CONNECTIONS .................................................................................................. 3-22

3.4.1 16-Mbit SDRAM Interface .......................................................................................................... 3-22

3.4.2 64-Mbit SDRAM Interface .......................................................................................................... 3-23

4. HOST INTERFACE............................................................................................................................................. 4-1

4.1 REGISTERS AND FIFO ........................................................................................................................... 4-1

4.2 HOST INTERFACE DESCRIPTION......................................................................................................... 4-3

4.2.1 Mailbox Interface ......................................................................................................................... 4-4

4.2.2 Host FIFO Interface ..................................................................................................................... 4-4

4.2.3 Host Bus Timing .......................................................................................................................... 4-7

4.2.4 Host Interface - DMA Demand Mode Timing ............................................................................... 4-9

4.2.5 Host Interface Pin Summary ...................................................................................................... 4-11

5. DESIGN CONSIDERATIONS ............................................................................................................................. 5-1

5.1 PC BOARD LAYOUT GUIDELINES......................................................................................................... 5-1

5.1.1 General Principles ....................................................................................................................... 5-1

5.1.2 Component Placement ................................................................................................................ 5-1

5.1.3 Signal Routing ............................................................................................................................. 5-1

5.1.4 Power........................................................................................................................................... 5-2

5.1.5 Ground Planes ............................................................................................................................. 5-2

5.1.6 Clock Oscillator Circuit................................................................................................................. 5-2

5.1.7 EMI Considerations for Standalone Modem Design .................................................................... 5-3

5.1.8 Optional Configurations ............................................................................................................... 5-3

5.1.9 DDP Specific................................................................................................................................ 5-3

Conexant

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