K4B4G1646Q View Datasheet(PDF) - Samsung
Part Name
Description
Manufacturer
K4B4G1646Q Datasheet PDF : 65 Pages
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K4B4G1646Q
datasheet
1. Ordering Information
[ Table 1 ] Samsung 4Gb DDR3L Q-die ordering information table
Organization
DDR3L-1066 (7-7-7)
DDR3L-1333 (9-9-9)3
256Mx16
K4B4G1646Q-HYF8
NOTE :
1. Speed bin is in order of CL-tRCD-tRP.
2. Backward compatible to DDR3L-1333(9-9-9), DDR3L-1066(7-7-7)
3. Backward compatible to DDR3L-1066(7-7-7)
K4B4G1646Q-HYH9
Preliminary Rev. 0.5
DDR3L SDRAM
DDR3L-1600 (11-11-11)2
K4B4G1646Q-HYK0
Package
96 FBGA
2. Key Features
[ Table 2 ] 4Gb DDR3 Q-die Speed bins
Speed
DDR3-800
6-6-6
tCK(min)
2.5
CAS Latency
6
tRCD(min)
15
tRP(min)
15
tRAS(min)
37.5
tRC(min)
52.5
DDR3-1066
7-7-7
1.875
7
13.125
13.125
37.5
50.625
DDR3-1333
9-9-9
1.5
9
13.5
13.5
36
49.5
DDR3-1600
Unit
11-11-11
1.25
ns
11
nCK
13.75
ns
13.75
ns
35
ns
48.75
ns
• JEDEC standard 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
• VDDQ = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
• 400 MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin,
667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin
• 8 Banks
• Programmable CAS Latency(posted CAS): 5,6,7,8,9,10,11
• Programmable Additive Latency: 0, CL-2 or CL-1 clock
• Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6
(DDR3-1066), 7 (DDR3-1333) and 8 (DDR3-1600)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting
address “000” only), 4 with tCCD = 4 which does not allow seamless
read or write [either On the fly using A12 or MRS]
• Bi-directional Differential Data-Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin
(RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than TCASE 85C, 3.9us at
85C < TCASE < 95 C
• Asynchronous Reset
• Package : 96 balls FBGA - x16
• All of Lead-Free products are compliant for RoHS
• All of products are Halogen-free
The 4Gb DDR3 SDRAM Q-die is organized as a 32Mbit x 16 I/Os x 8banks,
device. This synchronous device achieves high speed double-data-rate
transfer rates of up to 1600Mb/sec/pin (DDR3-1600) for general applica-
tions.
The chip is designed to comply with the following key DDR3 SDRAM fea-
tures such as posted CAS, Programmable CWL, Internal (Self) Calibration,
On Die Termination using ODT pin and Asynchronous Reset .
All of the control and address inputs are synchronized with a pair of exter-
nally supplied differential clocks. Inputs are latched at the crosspoint of dif-
ferential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-
ion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. The DDR3 device operates
with a single 1.35V(1.28V~1.45V) or 1.5V(1.425V~1.575V) power supply
and 1.35V(1.28V~1.45V) or 1.5V(1.425V~1.575V).
The 4Gb DDR3 Q-die device is available in 96ball FBGAs(x16).
NOTE : 1. This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device Operation & Timing
Diagram”.
2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
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