APA300-BG View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

APA300-BG

ProASIC PLUS® Flash Family FPGAs

Unspecified 

ProASICPLUS Flash Family FPGAs

Package Pins

GL

NPECL

PPECL

Physical I/O

Buffers

Std. Pad Cell

PECL Pad Cell

GLMX

GL

Std. Pad Cell

Std. Pad Cell

Global MUX

Configuration Tile

Configuration Tile

Global MUX B

OUT

External

Feedback

Global MUX A

OUT

CORE

Legend

Physical Pin

DATA Signals to the Core

DATA Signals to the PLL Block

DATA Signals to the Global MUX

Control Signals to the Global MUX

Note: When a signal from an I/O tile is connected to the core, it cannot be connected to the Global MUX at the same time.

Figure 1-15 • Input Connectors to ProASICPLUS Clock Conditioning Circuitry

Table 1-7 • Clock-Conditioning Circuitry MUX Settings

MUX

Datapath

FBSEL

1

Internal Feedback

2

Internal Feedback and Advance Clock Using FBDLY

3

External Feedback (EXTFB)

XDLYSEL

0

Feedback Unchanged

1

Deskew feedback by advancing clock by system delay

OBMUX

GLB

0

Primary bypass, no divider

1

Primary bypass, use divider

2

Delay Clock Using FBDLY

4

Phase Shift Clock by 0°

5

Reserved

6

Phase Shift Clock by +180°

7

Reserved

OAMUX

GLA

0

Secondary bypass, no divider

1

Secondary bypass, use divider

2

Delay Clock Using FBDLY

3

Phase Shift Clock by 0°

Comments

–0.25 to –4 ns in 0.25 ns increments

Fixed delay of -2.95 ns

+0.25 to +4 ns in 0.25 ns increments

+0.25 to +4 ns in 0.25 ns increments

v5.7

1-15

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