APA300-LG View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

APA300-LG

ProASIC PLUS® Flash Family FPGAs

Unspecified 

ProASICPLUS Flash Family FPGAs

÷1

Global MUX B OUT

÷n

133 MHz

÷m

÷1

180˚

PLL Core

0˚

D GLB

÷u

133 MHz

÷1

D

External Feedback

Global MUX A OUT

Figure 1-18 • Using the PLL to Delay the Input Clock

D

÷v

D GLA

÷1

Global MUX B OUT

÷n

133 MHz

÷m

÷1

180˚

PLL Core

0˚

D GLB

÷u

133 MHz

÷1

D

D

External Feedback

Global MUX A OUT

Figure 1-19 • Using the PLL to Advance the Input Clock

÷v

D GLA

1-18

v5.7

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