APA300-CQ View Datasheet(PDF) - Unspecified
Part Name
Description
Manufacturer
APA300-CQ Datasheet PDF : 174 Pages
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ProASICPLUS Flash Family FPGAs
DI<0:8>
LEVEL<0:7>
LGDEP<0:2>
WRB
WBLKB
RDB
RBLKB
PARODD
WCLKS
FIFO
(256x9)
Sync Write
and
Sync Read
Ports
DO <0:8>
WPE
RPE
FULL
EMPTY
EQTH
GEQTH
RESET
RCLKS
DI<0:8>
LEVEL<0:7>
LGDEP<0:2>
WRB
WBLKB
RDB
RBLKB
PARODD
WCLKS
FIFO
(256x9)
Sync Write
and
Async Read
Ports
DO <0:8>
WPE
RPE
FULL
EMPTY
EQTH
GEQTH
RESET
DI <0:8>
LEVEL <0:7>
LGDEP<0:2>
WRB
WBLKB
RDB
RBLKB
PARODD
FIFO
(256x9)
Async Write
and
Sync Read
Ports
DO <0:8>
WPE
RPE
FULL
EMPTY
EQTH
GEQTH
RESET
RCLKS
DI <0:8>
LEVEL <0:7>
LGDEP<0:2>
WRB
WBLKB
RDB
RBLKB
PARODD
FIFO
(256x9)
Async Write
and
Async Read
Ports
DO <0:8>
WPE
RPE
FULL
EMPTY
EQTH
GEQTH
RESET
Note: Each RAM block contains a multiplexer (called DMUX) for each output signal, increasing design efficiency. These DMUX cells do not
consume any core logic tiles and connect directly to high-speed routing resources between the RAM blocks. They are used when
RAM blocks are cascaded and are automatically inserted by the software tools.
Figure 1-22 • Basic FIFO Block Diagrams
Table 1-14 • Memory Block FIFO Interface Signals
FIFO Signal
Bits In/Out
Description
WCLKS
1
In
Write clock used for synchronization on write side
RCLKS
1
In
Read clock used for synchronization on read side
LEVEL <0:7>
8
In
Direct configuration implements static flag logic
RBLKB
1
In
Read block select (active Low)
RDB
1
In
Read pulse (active Low)
RESET
1
In
Reset for FIFO pointers (active Low)
WBLKB
1
In
Write block select (active Low)
DI<0:8>
9
In
Input data bits <0:8>, <8> will be generated parity if PARGEN is true
WRB
1
In
Write pulse (active Low)
FULL, EMPTY
2
Out FIFO flags. FULL prevents write and EMPTY prevents read
EQTH, GEQTH
2
Out EQTH is true when the FIFO holds the number of words specified by the LEVEL signal.
GEQTH is true when the FIFO holds (LEVEL) words or more
DO<0:8>
9
Out Output data bits <0:8>. <8> will be parity output if PARGEN is true.
RPE
1
Out Read parity error (active High)
WPE
LGDEP <0:2>
1
Out Write parity error (active High)
3
In
Configures DEPTH of the FIFO to 2 (LGDEP+1)
PARODD
1
In
Parity generation/detect – Even when Low, Odd when High
v5.7
1-25
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