NT7703 View Datasheet(PDF) - Novatek Microelectronics

Part Name

Description

Manufacturer

NT7703

160 Output LCD Segment/Common Driver

Novatek Microelectronics 

NT7703

Segment mode continued

Symbol

S/C

EIO1, EIO2

Y1 - Y160

Function

Segment mode/common mode selection pin

" When set to VDD level "H", segment mode is set

" When set to VSS level "L", common mode is set

Input/output pin for chip selection

" When L/R input is at VSS level “L”, EIO1 is set for output, and EIO2 is set for input

" When L/R input is at VDD level “H”, EIO1 is set for input, and EIO2 is set for output

" During output, it is set to “H” when LP* XCK is “H” and then after 160-bits of data have been read, it is

set to “L” for one cycle (from falling edge to falling edge of XCK), after which it returns to “H”

" During input, after the LP signal is input, the chip is selected while EI is set to “L”. After 160-bits of

data have been read, the chip is deselected

LCD driver output pins

These correspond directly to each bit of the data latch, one level (V0, V12, V43, or V5) is selected and output

Common mode

Symbol

VDD

VSS

V0R, V0L

V12R, V12L

V43R, V43L

V5R, V5L

EIO1

EIO2

LP

L/R

Function

Logic system power supply pin connects from +2.5 to +5.5V

Ground pin connects to 0V

Power supply pin for LCD driver voltage bias.

" Normally, the bias voltage used is set by a resistor divider

" Ensure that the voltages are set such that VSS ≤ V5 <V43 < V12 < V0

" To further reduce the differences between the output waveforms of the LCD driver output pins Y1 and

Y160, externally connect ViR and ViL (I = 0, 12, 43)

Bi-directional shift register shift data input/output pin

" Is an Output pin when L/R is at VSS level “L” and is an input pin when L/R is at VDD level “H”

" When EIO1 is used as an input pin, it will be pulled-down

" When EIO1 is used as an output pin, it won’t be pulled-down

Bi-directional shift register shift data input/output pin

" Is an Input pin when L/R is at VSS level “L” and is an output pin when L/R is at VDD level “H”

" When EIO2 is used as an input pin, it will be pulled-down

" When EIO2 is used as an output pin, it won’t be pulled-down

Bi-directional shift register shift clock pulse input pin

" Data is shifted on the falling edge of the clock pulse

Bi-directional shift register shift direction selection pin

" Data is shifted from Y160 to Y1 when it is set to VSS level “L”, and data is shifted from Y1 to Y160 when set

it is to VDD level “H”

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