SMJ55166-80 View Datasheet(PDF) - Austin Semiconductor

Part Name

Description

Manufacturer

SMJ55166-80

262144 BY 16-BIT MULTIPORT VIDEO RAM

Austin Semiconductor 

SMJ55166

262144 BY 16-BIT

MULTIPORT VIDEO RAM

SGMS057C – APRIL 1995 – REVISED JUNE 1997

column-address strobe (CAS)

CAS is a control input that latches the states of the column address and DSF to control DRAM and transfer

functions of the SMJ55166. CAS also acts as output enable for the DRAM output pins DQ0 – DQ15. During

transfer operations, address bits A0 – A8 are latched at the falling edge of CAS as the start position (tap) for the

serial-data output (SQ0 – SQ15).

output enable/transfer select (TRG)

TRG selects either DRAM or transfer operation as RAS falls. For DRAM operation, TRG must be held high as

RAS falls. During DRAM operation, TRG functions as an output enable for the DRAM output pins DQ0 – DQ15.

For transfer operation, TRG must be brought low before RAS falls.

write-mask select, write enable (WEL, WEU)

In DRAM operation, WEL enables data to be written to the lower byte (DQ0 – DQ7) and WEU enables data to

be written to the upper byte (DQ8 – DQ15) of the DRAM. Both WEL and WEU have to be held high together to

select the read mode. Bringing either or both WEL and WEU low selects the write mode. WEL and WEU are

also used to select the DRAM write-per-bit mode. Holding either or both WEL and WEU low on the falling edge

of RAS invokes the write-per-bit operation. The SMJ55166 supports both the nonpersistent write-per-bit mode

and the persistent write-per-bit mode.

special-function select (DSF)

The DSF input is latched on the falling edge of RAS or the first falling edge of CAS, similar to an address. DSF

determines which of the following functions is invoked on a particular cycle:

D CBR refresh with reset (CBR)

D CBR refresh with no reset (CBRN)

D CBR refresh with no reset and stop-point set (CBRS)

D Block write (BW)

D Load write-mask register (LMR) loading for the persistent write-per-bit mode

D Load color register (LCR) for the block-write mode

D Split-register-transfer (SRT) read

DRAM-data I/O, write-mask data (DQ0 – DQ15)

DRAM data is written or read through the common I/O DQ pins. The 3-state DQ-output buffers provide direct

TTL compatibility (no pul lup resistors) with a fanout of one Series 54 TTL load. Data out is the same polarity

as data in. The outputs are in the high-impedance (floating) state as long as either TRG or CAS is held high.

Data does not appear at the outputs until after both CAS and TRG have been brought low. The write mask is

latched into the device through the random DQ pins by the falling edge of RAS and is used on all write-per-bit

cycles. In a transfer operation, the DQ outputs remain in the high-impedance state for the entire cycle.

serial-data outputs (SQ0 – SQ15)

Serial data is read from SQ. SQ output buffers provide direct TTL compatibility (no pullup resistors) with a fanout

of one Series 54 TTL load. The serial outputs are in the high-impedance (floating) state while the serial-enable

pin, SE, is high. The serial outputs are enabled when SE is brought low.

serial clock (SC)

Serial data is accessed out of the data register from the rising edge of SC. The SMJ55166 is designed to work

with a wide range of clock duty cycles to simplify system design. There is no refresh requirement because the

data registers that comprise the SAM are static. There is also no minimum SC clock operating frequency.

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