TX9956C View Datasheet(PDF) - Toshiba

Part Name

Description

Manufacturer

TX9956C

RISC PROCESSOR

Toshiba 

Preliminary

TX9956CXBG

3. SYSTEM CONFIGURATION

3.1 TX9956C BLOCK DIAGRAM

TX9956C-533/600

TX99/H4 Core

Integer Execution Unit

Pipeline

Control A

Bypass

Pipeline

Pipeline

Control B

32 x 64

GPR

Instruction

Dispatcｈ Unit

Pipeline Queue

Inst. Dispatch

Instruction Decode

Instruction Buffer

Floating-Point Unit

Bypass

Pipeline

FP Single 0

MIPS-3D

32 x 64

FPR

FP Single 1

MIPS-3D

Return

Prediction

Stack

Branch

History

Table

32K Byte

Instruction Cache

4way set associative

MMU Control

48double entry

Joint-TLB

8 Entry

Micro-TLB

Debug Support Unit

(EJTAG)

32K Byte

Data Cache

4 way set associative

Write Buffer

Fill/Store

Buffer

Bus Interface Unit (MGB II)

Clock Generator

PLL

256K Byte

Secondary Cache

4way set associative

External Bus Interface Unit

MGB II bus to SysAD bus

Test Ciurcuit

JTAG etc.

Input Clock

64-bit / 32-bit

SysAD bus Interface

EJTAG

Interface

TX9956CXBG 2004-4-25 2

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