TX9956C View Datasheet(PDF) - Toshiba

Part Name

Description

Manufacturer

TX9956C

RISC PROCESSOR

Toshiba 

Preliminary

TX9956CXBG

3.2 BLOCK FUNCTION

TX99/H4 Core

True 64-bit microprocessor

32, 64-bit integer general purpose registers

32, 64-bit floating point general purpose registers

7-stage super-scalar pipeline

Instruction Set

MIPS64 ISA

3D Graphic’s instructions

On-chip 32-Kbyte Instruction Cache, 32-Kbyte Data Cache and 256KB Level2 Cache

4-way set associative and Lock function support : Primary cache

Data Cache: Write-back and Write-through support : Primary cache

256KB Secondary Cache

MMU

32-bit physical address space and 64-bit virtual address space

48-double-entry (even/odd) Joint TLB

8-entry Data TLB

IEEE754 compatible single and double precision FPU

Debug Support Unit (DSU) with EJTAG support

RP and Sleep mode

SysAD BUS I/F

Bus protocol conversion

It converts TX9956C Internal MGB II Read/Write request into outside SyAD Bus protocol.

Clock Generator

Generates the internal operating clock of the TX9901 from external crystal oscillator.

Debug Support Unit ( DSU )

EJTAG function support

Consists of an Enhanced JTAG (EJTAG) Module and a Debug Support Unit (DSU). It can be used

to provide single-step execution and hardware break-points for debugging processor systems.

EJTAG utilizes JTAG interface and extends the ability to access the inside register contents, host

system peripherals, and system memory.

TX9956CXBG 2004-4-25 3

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