LPC47N237-MD View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

LPC47N237-MD

3.3v I/O Controller for Port Replicators and Docking Stations

SMSC -> Microchip 

3.3v I/O Controller for Port Replicators and Docking Stations

PIN#

86

87

88

89

NAME

(NOTE 4.1)

nDSR

nRTS

nCTS

nDTR

DESCRIPTION

Active low Data Set Ready input for the

serial port. Handshake signal which notifies

the UART that the modem is ready to

establish the communication link. The CPU

can monitor the status of nDSR signal by

reading bit 5 of Modem Status Register

(MSR). A nDSR signal state change from

low to high after the last MSR read will set

MSR bit 1 to a 1. If bit 3 of Interrupt Enable

Register is set, the interrupt is generated

when nDSR changes state.

Note: Bit 5 of MSR is the complement of

nDSR.

Active low Request to Send outputs for the

Serial Port. Handshake output signal

notifies modem that the UART is ready to

transmit data. This signal can be

programmed by writing to bit 1 of the

Modem Control Register (MCR). The

hardware reset will reset the nRTS signal to

inactive mode (high). nRTS is forced

inactive during loop mode operation.

Active low Clear to Send inputs for the

serial port. Handshake signal which notifies

the UART that the modem is ready to

receive data. The CPU can monitor the

status of nCTS signal by reading bit 4 of

Modem Status Register (MSR). A nCTS

signal state change from low to high after

the last MSR read will set MSR bit 0 to a 1.

If bit 3 of the Interrupt Enable Register is

set, the interrupt is generated when nCTS

changes state. The nCTS signal has no

effect on the transmitter.

Note: Bit 4 of MSR is the complement of

nCTS.

Active low Data Terminal Ready outputs for

the serial port. Handshake output signal

notifies modem that the UART is ready to

establish data communication link. This

signal can be programmed by writing to bit

0 of Modem Control Register (MCR). The

hardware reset will reset the nDTR signal to

inactive mode (high). nDTR is forced

inactive during loop mode operation.

BUFFER

NAME

(NOTE 4.2)

I

O8

I

O8

PWR

WELL

(NOTE

4.3)

VCC

VCC

VCC

VCC

NOTES

Revision 0.3 (10-26-04)

Page 14

DATASHEET

SMSC DS – LPC47N237

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