LPC47N237-MD View Datasheet(PDF) - SMSC -> Microchip
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Description
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LPC47N237-MD Datasheet PDF : 138 Pages
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3.3v I/O Controller for Port Replicators and Docking Stations
TABLE OF CONTENTS
Chapter 1 General Description ........................................................................................................... 10
Chapter 2 Pin Configuration............................................................................................................... 11
Chapter 3 Pin Layout........................................................................................................................... 12
Chapter 4 Description of Pin Functions ............................................................................................. 13
4.1 Buffer Name Description ................................................................................................................... 18
4.2 Pins That Require External Resistors ............................................................................................... 19
Chapter 5 Block Diagram.................................................................................................................... 20
Chapter 6 Power/Clock Functionality................................................................................................ 21
6.1 3.3 Volt Operation / 5 Volt Tolerance ................................................................................................ 21
6.2 VCC Power........................................................................................................................................ 21
6.3 VTR Power ........................................................................................................................................ 21
6.3.1 Trickle Power Functionality .....................................................................................................................22
6.4 24 MHz Crystal.................................................................................................................................. 22
6.5 24 MHz Output .................................................................................................................................. 22
6.6 Internal PWRGOOD .......................................................................................................................... 22
6.7 Maximum Current Values.................................................................................................................. 23
6.8 Power Management Events (PME/SCI)............................................................................................ 23
Chapter 7 Functional Description....................................................................................................... 24
7.1 Super I/O Registers........................................................................................................................... 24
7.2 Host Processor Communication........................................................................................................ 24
7.3 LPC Interface .................................................................................................................................... 24
7.3.1 LPC Interface Signal Definition ...............................................................................................................25
LPC Cycles........................................................................................................................................................25
Field Definitions .................................................................................................................................................25
nLFRAME Usage ..............................................................................................................................................25
I/O Read and Write Cycles ................................................................................................................................26
DMA Read and Write Cycles.............................................................................................................................26
DMA Protocol ....................................................................................................................................................26
7.3.2 Power Management................................................................................................................................26
CLOCKRUN Protocol ........................................................................................................................................26
LPCPD Protocol ................................................................................................................................................26
SYNC Protocol ..................................................................................................................................................27
Typical Usage....................................................................................................................................................27
SYNC Timeout ..................................................................................................................................................27
SYNC Patterns and Maximum Number of SYNCS............................................................................................27
SYNC Error Indication .......................................................................................................................................28
I/O and DMA START Fields ..............................................................................................................................28
Reset Policy ......................................................................................................................................................28
7.3.3 LPC Transfers ........................................................................................................................................28
Wait State Requirements...................................................................................................................................28
Chapter 8 Serial Port (UART) ............................................................................................................ 29
8.1 Register Description .......................................................................................................................... 29
8.1.1 Receive Buffer Register (RB)..................................................................................................................29
8.1.2 Transmit Buffer Register (TB).................................................................................................................30
8.1.3 Interrupt Enable Register (IER)...............................................................................................................30
8.1.4 FIFO Control Register (FCR) ..................................................................................................................30
8.1.5 Interrupt Identification Register (IIR) .......................................................................................................31
8.1.6 Line Control Register (LCR)....................................................................................................................33
8.1.7 Modem Control Register (MCR) .............................................................................................................34
8.1.8 Line Status Register (LSR) .....................................................................................................................35
SMSC DS – LPC47N237
Page 3
DATASHEET
Revision 0.3 (10-26-04)
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