LPC47N237-MD View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

LPC47N237-MD

3.3v I/O Controller for Port Replicators and Docking Stations

SMSC -> Microchip 

3.3v I/O Controller for Port Replicators and Docking Stations

20.1.4

20.1.5

20.1.6

20.1.7

Forward Data Transfer Phase ...........................................................................................................129

Reverse-Idle Phase...........................................................................................................................129

Reverse Data Transfer Phase...........................................................................................................129

Output Drivers ...................................................................................................................................130

Chapter 21 XNOR-Chain Test Mode.............................................................................................. 135

21.1 Entering and Exiting Test Mode................................................................................................... 135

21.1.1 XNOR-Chain test mode can be entered as follows: ..........................................................................135

21.1.2 XNOR-Chain test mode can be exited as follows:.............................................................................135

21.2 Pin List of XNOR Chain ............................................................................................................... 136

21.3 Setup of XNOR Chain .................................................................................................................. 136

21.4 Testing Procedure........................................................................................................................ 136

Chapter 22 Package Outline ............................................................................................................ 138

LIST OF FIGURES

Figure 3.1 – LPC47N237 Pin Layout............................................................................................................................12

Figure 5.1 – LPC47N237 Block Diagram .....................................................................................................................20

Figure 8.1 - Serial Data ................................................................................................................................................33

Figure 11.1 A. Start Frame timing with source sampled a low pulse on IRQ1.......................................................68

Figure 11.2 B. Stop Frame Timing with Host using 17 SER_IRQ sampling period ...............................................68

Figure 12.1 – nCLKRUN System Implementation Example .........................................................................................73

Figure 12.2 – Clock Start Illustration ............................................................................................................................74

Figure 13.1 - GPIO Function Illustration.......................................................................................................................76

Figure 15.1 – SMBus Isolation Switch..........................................................................................................................83

Figure 15.2 - GPIO Transition Cases ...........................................................................................................................86

Figure 15.3 – Sample Representation of nSMBINT Assertion Logic ............................................................................88

Figure 20.1 - POWER-UP TIMING.............................................................................................................................122

Figure 20.2 – 24MHz_OUT CLOCK TIMING .............................................................................................................123

Figure 20.3 – PCI CLOCK TIMING ............................................................................................................................123

Figure 20.4 - RESET TIMING ....................................................................................................................................123

Figure 20.5 – Output Timing Measurement Conditions, LPC Signals ........................................................................124

Figure 20.6 – Input Timing Measurement Conditions, LPC Signals ...........................................................................124

Figure 20.7 – LPC I/O Write .......................................................................................................................................124

Figure 20.8 – LPC I/O Read.......................................................................................................................................125

Figure 20.9 – DMA Request Assertion Through nLDRQ............................................................................................125

Figure 20.10 – LPC DMA Write (First Byte) ...............................................................................................................125

Figure 20.11 – LPC DMA Read (First Byte) ...............................................................................................................125

Figure 20.12 – EPP 1.9 Data or Address Write Cycle ................................................................................................126

Figure 20.13 – EPP 1.9 Data or Address Read Cycle................................................................................................127

Figure 20.14 – EPP 1.7 Data or Address Write Cycle ................................................................................................128

Figure 20.15 – EPP 1.7 Data or Address Read Cycle................................................................................................128

Figure 20.16 – Parallel Port FIFO Timing...................................................................................................................130

Figure 20.17 - ECP Parallel Port Forward Timing ......................................................................................................131

Figure 20.18 - ECP Parallel Port Reverse Timing ......................................................................................................132

Figure 20.19 – SER_IRQ Setup and Hold Time.........................................................................................................133

Figure 20.20 – Serial Port Data..................................................................................................................................133

Figure 20.21 – SMBus Timing....................................................................................................................................134

Figure 21.1 – XNOR-CHAIN TEST STRUCTURE .....................................................................................................135

Figure 22.1 – 100 Pin TQFP Package Outline ...........................................................................................................138

LIST OF TABLES

Table 2.1 – LPC47N237 Pin Configuration ..................................................................................................................11

Table 4.1 – Pin Description ..........................................................................................................................................13

Table 7.1 - Super I/O Block Addresses ........................................................................................................................24

SMSC DS – LPC47N237

Page 7

DATASHEET

Revision 0.3 (10-26-04)

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