LTC1416 View Datasheet(PDF) - Linear Technology

Part Name

Description

Manufacturer

LTC1416

Low Power 14-Bit, 400ksps Sampling ADC

Linear Technology 

LTC1416

APPLICATIONS INFORMATION

reference amplifier compensation pin, REFCOMP (Pin 4),

must be bypassed with a capacitor to ground. The refer-

ence amplifier is stable with capacitors of 1µF or greater.

For the best noise performance, a 22µF ceramic or 22µF

tantalum in parallel with a 0.1µF ceramic is recommended.

The VREF pin can be driven with a DAC or other means

shown in Figure 9. This is useful in applications where the

peak input signal amplitude may vary. The input span of

the ADC can then be adjusted to match the peak input

signal, maximizing the signal-to-noise ratio. The filtering

of the internal LTC1416 reference amplifier will limit the

bandwidth and settling time of this circuit. A settling time

of 5ms should be allowed for after a reference adjustment.

80

70

60

50

40

30

20

10

0

1k

10k

100k

1M 2M

INPUT FREQUENCY (Hz)

1416 G09

Figure 10a. CMRR vs Input Frequency

LTC1450

ANALOG

INPUT

1.25V TO 3V

22µF

1 AIN+

2 AIN–

3

LTC1416

VREF

4

REFCOMP

5

AGND

1416 F09

Figure 9. Driving VREF with a DAC

ANALOG INPUT

±2.5V

0V TO 5V

22µF

1 AIN+

2 AIN–

3 VREF

LTC1416

4

REFCOMP

5

AGND

1416 F10b

Figure 10b. Selectable 0V to 5V or ±2.5V Input Range

Differential Inputs

The LTC1416 has a unique differential sample-and-hold

circuit that allows rail-to-rail inputs. The ADC will always

convert the difference of AIN+ – AIN– independent of the

common mode voltage. The common mode rejection

holds up to extremely high frequencies (see Figure 10a).

The only requirement is that both inputs cannot exceed the

AVDD or AVSS power supply voltages. Integral nonlinearity

errors (INL) and differential nonlinearity errors (DNL) are

independent of the common mode voltage, however, the

bipolar zero error (BZE) will vary. The change in BZE is

typically less than 0.1% of the common mode voltage.

Dynamic performance is also affected by the common

mode voltage. THD will degrade as the inputs approach

either power supply rail, from 90dB with a common mode

of 0V to 79dB with a common mode of 2.5V or – 2.5V.

Differential inputs allow greater flexibility for accepting

different input ranges. Figure 10b shows a circuit that

converts a 0V to 5V analog input signal with no additional

translation circuitry.

Full-Scale and Offset Adjustment

Figure 11a shows the ideal input/output characteristics for

the LTC1416. The code transitions occur midway between

successive integer LSB values (i.e., – FS + 0.5LSB, – FS +

1.5LSB, – FS + 2.5LSB, . . . FS – 1.5LSB, FS – 0.5LSB). The

output is two’s complement binary with 1LSB = FS –

(– FS)/16384 = 5V/16384 = 305.2µV.

In applications where absolute accuracy is important,

offset and full-scale errors can be adjusted to zero. Offset

error must be adjusted before full-scale error. Figure 11b

shows the extra components required for full-scale error

adjustment. Zero offset is achieved by adjusting the offset

applied to the AIN– input. For zero offset error, apply

– 152µV (i.e., – 0.5LSB) at AIN+ and adjust the offset at the

AIN– input until the output code flickers between 0000

12

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