CXD2529Q View Datasheet(PDF) - Sony Semiconductor

Part Name

Description

Manufacturer

CXD2529Q

CD Digital Signal Processor

Sony Semiconductor 

CXD2529Q

Peak meter

XLAT

SQCK

SQSO

(Peak meter)

L0 L1 L2 L3 L4 L5 L6 L7 R0 R1 R2 R3 R4 R5 R6 R7

The LSI is set to peak detection mode by setting SOCT = 0, SL1 = 0 and SL0 = 1 with the $8X and $BX

commands. In peak detection mode, the SQSO output is connected to the peak detection register. The

maximum PCM data values (absolute value, upper 8 bits) for the left and right channels can be read out from

SQSO by inputting 16 clocks to SQCK. Peak detection is not performed while inputting to SQCK, and the peak

detection register does not change during readout. This SQCK input is judged using a retriggerable

monostable multivibrator with a time constant of 270 to 400µs. Set the time for which SQCK input is high to

270µs or less. Peak detection restarts from 270 to 400µs after SQCK input.

The peak detection register is reset to zero for each readout (16 clocks input to SQCK). The maximum value

during peak detection mode is detected and held in this condition until the next readout. When setting the LSI

to peak detection mode, perform readout one time initially to reset the peak detection register.

Pre-value hold and average value interpolation data are also detected by peak detection.

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