IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO™
64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
WCLK
tDS
D0 - D7
WEN
RCLK
D0 (first valid write)
D1
tENS
tSKEW1
(1)
tFRL
tREF
EF
MILITARY AND COMMERCIAL TEMPERATURE RANGES
D2
D3
REN
Q0 - Q7
OE
tA
tOLZ
tOE
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timing apply only at the Empty Boundry (EF = LOW).
Figure 5. First Data Word Latency Timing
tA
D0
D1
2680 drw 07
5.12
10