MC44827B View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
MC44827B Datasheet PDF : 8 Pages
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MC44827/27B
Pin
1
2
3
4
5
6
7
8
9
10,11,12,13
14
15
16
Symbol
DA
CL
XTAL
Amp In
VTUN
VCC2
VCC1
HF In
Gnd
B0 to B3
VCC3
Lock
EN
PIN FUNCTION DESCRIPTION
Description
3–wire bus data input
3–wire bus clock input
Crystal oscillator (3.2 MHz or 4 MHz)
Negative operational amplifier input and phase comparator output
Operational amplifier output which provides the tuning voltage
Operational amplifier positive supply (33 V)
Positive supply of the circuit (5 V)
Asymmetrical HF input
Ground
PNP Band buffer outputs
Positive supply for integrated band buffers (12 V)
Lock detector output
3–wire bus enable input
Data Format and Bus Receiver
The circuit is controlled by a 3–wire bus via Data (DA),
Clock (CL), and Enable (EN) inputs. The Data and Clock
inputs may be shared with other inputs on the I2C–Bus while
the Enable is a separate signal. The circuit is compatible with
18 and 19 bit data transmission and also has a mode for
34 bit transmission for test and additional features.
The 3–wire bus receiver receives data for the internal shift
register after the positive going edge of the EN–signal. The
data is transmitted to the band buffers on the negative going
edge of the clock pulse 4 (signal DTB1).
18 and 19 Bit Data Transmission
The programmable divider may receive a division ratio
coded by a 14 bit (18 bit transmission) or 15 bit (19 bit
transmission). The data is transmitted to the programmable
divider (latches A) on the negative going edge of clock pulse
19 or on the negative edge of the EN–signal if EN goes down
after the 18th clock pulse (signal DTF). If the programmable
divider receives a 14 bit byte, its MSB (bit N14) is internally
reset. The reset pulse is generated only if EN goes negative
after the 18th clock pulse (signal RL).
34 Bit Data Transmission
(For Test and Additional Features)
In the test mode, the programmable divider receives a 15
bit byte and the data is transferred to latches A on the
negative edge of clock pulse 19 (signal DTF). The
information for test is received on clock pulses 20 to 26 and
transmitted to the latches on the negative edge of pulse 34
(signal DTB2). These latches have a power–on reset. The
power–on reset sets the programmable divider to a counting
ratio of 256 or higher and resets the corresponding latches to
the test bits T0 to T6 (signal POR). The bus receiver is not
disturbed if the data format is wrong. Unused bits are
ignored. If for example the Enable signal goes low after clock
pulse 9, bits one to four are accepted as valid buffer
information and the other bits are ignored. If more than 34
bits are received, bit 35 and the following are ignored.
Figure 5. Bus Timing Diagram
Standard Bus Protocol 18 or 19 Bit
Data
1
45
18 19
Clock
Buffers
Counting Ratio
Enable
Bus Protocol for Test and Features
1
45
19 20
26 27
33 34
B3 B2 B1 B0 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 T6 T5 T4 T3 T2 T1 T0 X7 X6 X5 X4 X3 X2 X1 X0
Buffers
Counting Ratio
Test & Features
Not Used
MOTOROLA ANALOG IC DEVICE DATA
5
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