AT90PWM216 View Datasheet(PDF) - Atmel Corporation
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AT90PWM216 Datasheet PDF : 28 Pages
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8. Errata AT90PWM216/316
8.1 Revision C
• DAC Driver linearity above 3.6V
1. DAC Driver linearity above 3.6V
With 5V VCC, the DAC driver linearity is poor when DAC output level is above VCC-1V. At 5V, DAC output for
1023 will be around 5V - 40mV.
Work around:
Use, when Vcc=5V, VREF below VCC-1V
Or, when VREF=VCC=5V, do not uses codes above 800.
8.2 Revision B
• DAC Driver linearity above 3.6V
• PSC OCRxx Register update according to PLOCK2 usage
1. DAC Driver linearity above 3.6V
With 5V VCC, the DAC driver linearity is poor when DAC output level is above VCC-1V. At 5V, DAC output for
1023 will be around 5V - 40mV.
Work around:
Use, when Vcc=5V, VREF below VCC-1V
Or, when VREF=VCC=5V, do not uses codes above 800.
2. PSC OCRxx Register update according to PLOCK2 usage
If the PSC is clocked from PLL, and if PLOCK2 bit is changed at the same time as PSC end of cycle occurs,
and if OCRxx registers contents have been changed, then the updated OCRxx registers contents are not
predictable.
The cause is a synchronization issue between two registers in two different clock domains (PLL clock which
clocks PSC and CPU clock).
Workaround:
Enable the PSC end of cycle interrupt.
At the beginning of PSC EOC interrupt vector, change PLOCK value (OCRxx registers can be updated outside
the interrupt vector).
This process guarantees that UPDATE and PLOCK actions will not occur at the same moment.
AT90PWM216/316 [DATASHEET] 23
7710HS–AVR–07/2013
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