AT90PWM216 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
AT90PWM216 Datasheet PDF : 28 Pages
| |||
3.1 Block Diagram
Figure 3-1. Block Diagram
16Kx8 Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Control Lines
Program
Counter
Data Bus 8-bit
Status
and Control
32 x 8
General
Purpose
Registrers
ALU
Data
SRAM
1024 bytes
EEPROM
512 bytes
I/O Lines
Interrupt
Unit
SPI
Unit
Watchdog
Timer
3 Analog
Comparators
DALI USART
Timer 0
Timer 1
ADC
DAC
PSC 2/1/0
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are
directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one
single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
The AT90PWM216/316 provides the following features: 16K bytes of In-System Programmable Flash with Read-
While-Write capabilities, 512 bytes EEPROM, 1024 bytes SRAM, 53 general purpose I/O lines, 32 general purpose
working registers, three Power Stage Controllers, two flexible Timer/Counters with compare modes and PWM, one
USART with DALI mode, an 11-channel 10-bit ADC with two differential input stage with programmable gain, a 10-
bit DAC, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, an On-chip Debug system
and four software selectable power saving modes.
The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports and interrupt system to con-
tinue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other
chip functions until the next interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all
I/O modules except ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Res-
AT90PWM216/316 [DATASHEET]
8
7710HS–AVR–07/2013
Share Link: 