CDK2000 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CDK2000

Fractional-N Clock Synthesizer & Clock Multiplier

Cirrus Logic 

CS2000-CP

PLL PERFORMANCE PLOTS

Test Conditions (unless otherwise specified): VD = 3.3 V; TA = 25 °C; CL = 15 pF; fCLK_OUT = 12.288 MHz;

fCLK_IN = 12.288 MHz; Sample size = 10,000 points; Base Band Jitter (100 Hz to 40 kHz); AuxOutSrc[1:0] = 11.

10,000

1,000

1 Hz Bandwidth

128 Hz Bandwidth

100

10

1

0.1

1

10

100

1,000

10,000

Input Jitter Frequency (Hz)

Figure 2. CLK_IN Sinusoidal Jitter Tolerance

Samples size = 2.5M points; Base Band Jitter (100Hz to 40kHz).

10

1 Hz Bandwidth

128 Hz Bandwidth

0

-10

-20

-30

-40

-50

-60

1

10

100

1000

10000

Input Jitter Frequency (Hz)

Figure 3. CLK_IN Sinusoidal Jitter Transfer

Samples size = 2.5M points; Base Band Jitter (100Hz to 40kHz).

1000

1 Hz Bandwidth

128 Hz Bandwidth

100

10

Unlock

1

Unlock

0.1

0.01

0.01

0.1

1

10

100

1000

Input Jitter Level (nsec)

Figure 4. CLK_IN Random Jitter Rejection and Tolerance

DS761F3

9

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