KS8765CLX View Datasheet(PDF) - Micrel

Part Name

Description

Manufacturer

KS8765CLX

Integrated 5-Port 10/100 Managed Ethernet Switch with Gigabit GMII/RGMII and MII/RMII Interfaces

Micrel 

Micrel, Inc.

KSZ8765CLX

List of Figures

Figure 1. KSZ8765CLX Functional Block Diagram............................................................................................................... 1

Figure 2. 80-Pin LQFP ........................................................................................................................................................ 11

Figure 3. Typical Straight Cable Connection ...................................................................................................................... 22

Figure 4. Typical Crossover Cable Connection .................................................................................................................. 22

Figure 5. Auto-Negotiation and Parallel Operation ............................................................................................................. 23

Figure 6. Destination Adddress Look-up and Resolution Flow Chart ................................................................................. 29

Figure 7. EEE Transmit and Receive Signaling Paths ....................................................................................................... 31

Figure 8. Traffic Activity and EEE LPI Operations .............................................................................................................. 33

Figure 9. SPI Access Timing............................................................................................................................................... 36

Figure 10. SPI Multiple Access Timing ................................................................................................................................. 37

Figure 11. 802.1p Priority Field Format ................................................................................................................................ 44

Figure 12. Tail Tag Frame Format ........................................................................................................................................ 47

Figure 13. ACL Format.......................................................................................................................................................... 54

Figure 14. Interface and Register Mapping........................................................................................................................... 57

Figure 15. ACL Table Access ............................................................................................................................................. 111

Figure 16. GMII Signals Timing Diagram ............................................................................................................................ 140

Figure 17. RGMII v2.0 Specification ................................................................................................................................... 141

Figure 18. MAC Mode MII Timing – Data Received from MII ............................................................................................. 142

Figure 19. MAC Mode MII Timing – Data Transmitted from MII ......................................................................................... 142

Figure 20. PHY Mode MII Timing – Data Received from MII.............................................................................................. 143

Figure 21. PHY Mode MII Timing – Data Transmitted from MII.......................................................................................... 143

Figure 22. RMII Timing – Data Received from RMII ........................................................................................................... 144

Figure 23. RMII Timing – Data Transmitted to RMII ........................................................................................................... 144

Figure 24. SPI Input Timing ................................................................................................................................................ 145

Figure 25. SPI Output Timing.............................................................................................................................................. 146

Figure 26. Auto-Negotiation Timing Diagram...................................................................................................................... 147

Figure 27. MDC/MDIO Timing Diagram .............................................................................................................................. 148

Figure 28. Reset Timing Diagram ....................................................................................................................................... 149

Figure 29. Recommended Reset Circuit ............................................................................................................................. 150

Figure 30. Recommended Circuit for Interfacing with CPU/FPGA Reset........................................................................... 150

Figure 31. 80-Pin LQFP ...................................................................................................................................................... 152

July 23, 2014

9

Revision 1.0

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