PIC16F54-I(2004) View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16F54-I
(Rev.:2004)

Flash-Based, 8-Bit CMOS Microcontroller Series

Microchip Technology 

PIC16F5X

2.1 Clocking Scheme/Instruction

Cycle

The clock input (OSC1/CLKIN pin) is internally divided

by four to generate four non-overlapping quadrature

clocks, namely Q1, Q2, Q3 and Q4. Internally, the

Program Counter (PC) is incremented every Q1 and

the instruction is fetched from program memory and

latched into the instruction register in Q4. It is decoded

and executed during the following Q1 through Q4. The

clocks and instruction execution flow are shown in

Figure 2-2 and Example 2-1.

FIGURE 2-2:

CLOCK/INSTRUCTION CYCLE

2.2 Instruction Flow/Pipelining

An instruction cycle consists of four Q cycles (Q1, Q2,

Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle,

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the Program Counter to change (e.g., GOTO),

then two cycles are required to complete the instruction

(Example 2-1).

A fetch cycle begins with the Program Counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the instruction register in cycle Q1. This instruction

is then decoded and executed during the Q2, Q3 and

Q4 cycles. Data memory is read during Q2 (operand

read) and written during Q4 (destination write).

OSC1

Q1

Q2

Q3

Q4

PC

OSC2/CLKOUT

(RC mode)

Q1 Q2 Q3 Q4

PC

Fetch INST (PC)

Execute INST (PC - 1)

Q1 Q2 Q3 Q4

PC+1

Fetch INST (PC + 1)

Execute INST (PC)

Q1 Q2 Q3 Q4

PC+2

Fetch INST (PC + 2)

Execute INST (PC + 1)

Internal

phase

clock

EXAMPLE 2-1: INSTRUCTION PIPELINE FLOW

1. MOVLW H'55'

2. MOVWF PORTB

3. CALL SUB_1

4. BSF PORTA, BIT3

Fetch 1

Execute 1

Fetch 2

Execute 2

Fetch 3

Execute 3

Fetch 4

Flush

Fetch SUB_1 Execute SUB_1

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction

is “flushed” from the pipeline, while the new instruction is being fetched and then executed.

DS41213C-page 12

 2004 Microchip Technology Inc.

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