SCA103T View Datasheet(PDF) - VTI technologies

Part Name

Description

Manufacturer

SCA103T

THE SCA103T DIFFERENTIAL INCLINOMETER SERIES

VTI technologies 

SCA103T Series

MASTER

MICROCONTROLLER

DATA OUT (MOSI)

DATA IN (MISO)

SERIAL CLOCK (SCK)

SS0

SS1

SS2

SS3

SLAVE

SI

SO

SCK

CS

SI

SO

SCK

CS

SI

SO

SCK

CS

SI

SO

SCK

CS

Figure 9.

Typical SPI connection

The SPI interface in VTI products is designed to support any micro controller that uses SPI bus.

Communication can be carried out by software or hardware based SPI. Please note that in the

case of hardware based SPI, the received acceleration data is 11 bits. The data transfer uses the

following 4-wire interface:

MOSI

MISO

SCK

CSB

master out slave in

master in slave out

serial clock

chip select (low active)

µP → SCA103T

SCA103T → µP

µP → SCA103T

µP → SCA103T

Each transmission starts with a falling edge of CSB and ends with the rising edge. During

transmission, commands and data are controlled by SCK and CSB according to the following rules:

• commands and data are shifted; MSB first, LSB last

• each output data/status bits are shifted out on the falling edge of SCK (MISO line)

• each bit is sampled on the rising edge of SCK (MOSI line)

• after the device is selected with the falling edge of CSB, an 8-bit command is received. The

command defines the operations to be performed

• the rising edge of CSB ends all data transfer and resets internal counter and command register

• if an invalid command is received, no data is shifted into the chip and the MISO remains in high

impedance state until the falling edge of CSB. This reinitializes the serial communication.

• data transfer to MOSI continues immediately after receiving the command in all cases where

data is to be written to SCA103T’s internal registers

• data transfer out from MISO starts with the falling edge of SCK immediately after the last bit of

the SPI command is sampled in on the rising edge of SCK

• maximum SPI clock frequency is 500kHz

• maximum data transfer speed for RDAX and RDAY is 5300 samples per sec / channel

SPI command can be either an individual command or a combination of command and data. In the

case of combined command and data, the input data follows uninterruptedly the SPI command and

the output data is shifted out in parallel with the input data.

The SPI interface uses an 8-bit instruction (or command) register. The list of commands is given in

Table below.

VTI Technologies Oy

www.vti.fi

Subject to changes

Doc.Nr. 8261700

11/19

Rev.A

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