MPC8541CPXAJD(2006) View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MPC8541CPXAJD
(Rev.:2006)

PowerQUICC™ III Integrated Communications Processor Hardware Specifications

Freescale Semiconductor 

Overview

1 Overview

The following section provides a high-level overview of the MPC8541E features. Figure 1 shows the

major functional units within the MPC8541E.

.

DDR

SDRAM

DDR SDRAM Controller

I2C Controller

Security

Engine

256 Kbyte

L2 Cache/

SRAM

e500 Core

GPIO

32b

DUART

Local Bus Controller

e500

Coherency

Module

Core Complex

Bus

32-Kbyte L1 32-Kbyte L1

I Cache

D Cache

IRQs

Programmable

Interrupt Controller

CPM

Serial

DMA

FCC

FCC

ROM

OCeaN

64/32b PCI Controller

0/32b PCI Controller

MIIs/RMIIs

I-Memory

DPRAM

DMA Controller

I/Os

RISC

SPI

Engine

I2C Parallel I/O

Baud Rate

Generators

10/100/1000 MAC

10/100/1000 MAC

MII, GMII, TBI,

RTBI, RGMIIs

Timers

CPM

Interrupt

Controller

Figure 1. MPC8541E Block Diagram

1.1 Key Features

The following lists an overview of the MPC8541E feature set.

• Embedded e500 Book E-compatible core

— High-performance, 32-bit Book E-enhanced core that implements the PowerPC architecture

— Dual-issue superscalar, 7-stage pipeline design

— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection

— Lockable L1 caches—entire cache or on a per-line basis

— Separate locking for instructions and data

— Single-precision floating-point operations

— Memory management unit especially designed for embedded applications

— Enhanced hardware and software debug support

— Dynamic power management

— Performance monitor facility

MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4

2

Freescale Semiconductor

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