MPC8541CPXAJD(2006) View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MPC8541CPXAJD
(Rev.:2006)

PowerQUICC™ III Integrated Communications Processor Hardware Specifications

Freescale Semiconductor 

Overview

• Security Engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,

802.11i, iSCSI, and IKE processing. The Security Engine contains 4 Crypto-channels, a Controller,

and a set of crypto Execution Units (EUs). The Execution Units are:

— Public Key Execution Unit (PKEU) supporting the following:

– RSA and Diffie-Hellman

– Programmable field size up to 2048-bits

– Elliptic curve cryptography

– F2m and F(p) modes

– Programmable field size up to 511-bits

— Data Encryption Standard Execution Unit (DEU)

– DES, 3DES

– Two key (K1, K2) or Three Key (K1, K2, K3)

– ECB and CBC modes for both DES and 3DES

— Advanced Encryption Standard Unit (AESU)

– Implements the Rinjdael symmetric key cipher

– Key lengths of 128, 192, and 256 bits.Two key

– ECB, CBC, CCM, and Counter modes

— ARC Four execution unit (AFEU)

– Implements a stream cipher compatible with the RC4 algorithm

– 40- to 128-bit programmable key

— Message Digest Execution Unit (MDEU)

– SHA with 160-bit or 256-bit message digest

– MD5 with 128-bit message digest

– HMAC with either algorithm

— Random Number Generator (RNG)

— 4 Crypto-channels, each supporting multi-command descriptor chains

– Static and/or dynamic assignment of crypto-execution units via an integrated controller

– Buffer size of 256 Bytes for each execution unit, with flow control for large data sizes

• High-performance RISC CPM

— Two full-duplex fast communications controllers (FCCs) that support the following protocol:

– IEEE802.3/Fast Ethernet (10/100)

— Serial peripheral interface (SPI) support for master or slave

— I2C bus controller

— General-purpose parallel ports—16 parallel I/O lines with interrupt capability

• 256 Kbytes of on-chip memory

— Can act as a 256-Kbyte level-2 cache

— Can act as a 256-Kbyte or two 128-Kbyte memory-mapped SRAM arrays

— Can be partitioned into 128-Kbyte L2 cache plus 128-Kbyte SRAM

— Full ECC support on 64-bit boundary in both cache and SRAM modes

MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

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