MPC8541CPXAJD(2006) View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MPC8541CPXAJD
(Rev.:2006)

PowerQUICC™ III Integrated Communications Processor Hardware Specifications

Freescale Semiconductor 

Overview

— SRAM operation supports relocation and is byte-accessible

— Cache mode supports instruction caching, data caching, or both

— External masters can force data to be allocated into the cache through programmed memory

ranges or special transaction types (stashing)

— Eight-way set-associative cache organization (1024 sets of 32-byte cache lines)

— Supports locking the entire cache or selected lines

– Individual line locks set and cleared through Book E instructions or by externally mastered

transactions

— Global locking and flash clearing done through writes to L2 configuration registers

— Instruction and data locks can be flash cleared separately

— Read and write buffering for internal bus accesses

• Address translation and mapping unit (ATMU)

— Eight local access windows define mapping within local 32-bit address space

— Inbound and outbound ATMUs map to larger external address spaces

– Three inbound windows plus a configuration window on PCI

– Four inbound windows

– Four outbound windows plus default translation for PCI

• DDR memory controller

— Programmable timing supporting first generation DDR SDRAM

— 64-bit data interface, up to MHz data rate

— Four banks of memory supported, each up to 1 Gbyte

— DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports

— Full ECC support

— Page mode support (up to 16 simultaneous open pages)

— Contiguous or discontiguous memory mapping

— Sleep mode support for self refresh DDR SDRAM

— Supports auto refreshing

— On-the-fly power management using CKE signal

— Registered DIMM support

— Fast memory access via JTAG port

— 2.5-V SSTL2 compatible I/O

• Programmable interrupt controller (PIC)

— Programming model is compliant with the OpenPIC architecture

— Supports 16 programmable interrupt and processor task priority levels

— Supports 12 discrete external interrupts

— Supports 4 message interrupts with 32-bit messages

— Supports connection of an external interrupt controller such as the 8259 programmable

interrupt controller

MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4

4

Freescale Semiconductor

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