MPC8541CPXAJD(2006) View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
MPC8541CPXAJD
(Rev.:2006)
(Rev.:2006)
Freescale Semiconductor
MPC8541CPXAJD Datasheet PDF : 84 Pages
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Overview
– 1000 Mbps IEEE 802.3z TBI
– 10/100/1000 Mbps RGMII/RTBI
— Full- and half-duplex support
— Buffer descriptors are backwards compatible with MPC8260 and MPC860T 10/100
programming models
— 9.6-Kbyte jumbo frame support
— RMON statistics support
— 2-Kbyte internal transmit and receive FIFOs
— MII management interface for control and status
— Programmable CRC generation and checking
• OCeaN switch fabric
— Three-port crossbar packet switch
— Reorders packets from a source based on priorities
— Reorders packets to bypass blocked packets
— Implements starvation avoidance algorithms
— Supports packets with payloads of up to 256 bytes
• Integrated DMA controller
— Four-channel controller
— All channels accessible by both local and remote masters
— Extended DMA functions (advanced chaining and striding capability)
— Support for scatter and gather transfers
— Misaligned transfer capability
— Interrupt on completed segment, link, list, and error
— Supports transfers to or from any local memory or I/O port
— Selectable hardware-enforced coherency (snoop/no-snoop)
— Ability to start and flow control each DMA channel from external 3-pin interface
— Ability to launch DMA from single write transaction
• PCI Controllers
— PCI 2.2 compatible
— One 64-bit or two 32-bit PCI ports supported at 16 to 66 MHz
— Host and agent mode support, 64-bit PCI port can be host or agent, if two 32-bit ports, only one
can be an agent
— 64-bit dual address cycle (DAC) support
— Supports PCI-to-memory and memory-to-PCI streaming
— Memory prefetching of PCI read accesses
— Supports posting of processor-to-PCI and PCI-to-memory writes
— PCI 3.3-V compatible
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
6
Freescale Semiconductor
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