FM24CL64B(2014) View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

FM24CL64B
(Rev.:2014)

64-Kbit (8K × 8) Serial (I2C) F-RAM

Cypress Semiconductor 

FM24CL64B

Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the

device. These user guidelines are not tested.

Storage temperature ................................ –55 C to +125 C

Maximum junction temperature ................................... 95 C

Supply voltage on VDD relative to VSS .........–1.0 V to +5.0 V

Input voltage .......... –1.0 V to + 5.0 V and VIN < VDD + 1.0 V

DC voltage applied to outputs

in High-Z state .................................... –0.5 V to VDD + 0.5 V

Transient voltage (< 20 ns) on

any pin to ground potential ................. –2.0 V to VDD + 2.0 V

Package power dissipation

capability (TA = 25 °C) ................................................. 1.0 W

Surface mount lead soldering

temperature (10 seconds) ....................................... +260 C

Electrostatic Discharge Voltage

Human Body Model (AEC-Q100-002 Rev. E) ..................... 4 kV

Charged Device Model (AEC-Q100-011 Rev. B) ............. 1.25 kV

Machine Model (AEC-Q100-003 Rev. E) ............................ 300 V

Latch-up current .................................................... > 140 mA

* Exception: The "VIN < VDD + 1.0 V" restriction does not apply

to the SCL and SDA inputs.

Operating Range

Range Ambient Temperature (TA)

VDD

Industrial

–40 C to +85 C

2.7 V to 3.65 V

DC Electrical Characteristics

Over the Operating Range

Parameter

Description

VDD

Power supply

IDD

Average VDD current

ISB

Standby current

ILI

ILO

VIH

VIL

VOL

Rin[2]

VHYS[3]

Input leakage current

(Except WP and A2-A0)

Input leakage current

(for WP and A2-A0)

Output leakage current

Input HIGH voltage

Input LOW voltage

Output LOW voltage

Input resistance (WP, A2-A0)

Input hysteresis

Test Conditions

Min

2.7

SCL toggling

fSCL = 100 kHz

–

between

VDD – 0.3 V and VSS,

other inputs VSS or

fSCL = 400 kHz

fSCL = 1 MHz

–

–

VDD – 0.3 V.

SCL = SDA = VDD. All

–

other inputs VSS or

VDD. Stop command

issued.

VSS < VIN < VDD

–1

Typ [1]

3.3

–

–

–

3

–

VSS < VIN < VDD

–1

–

VSS < VIN < VDD

IOL = 3 mA

For VIN = VIL (Max)

For VIN = VIH (Min)

–1

–

0.7 × VDD

–

– 0.3

–

–

–

40

–

1

–

0.05 × VDD

–

Max Unit

3.65

V

100

A

170

A

300

A

6

A

+1

A

+100

A

+1

A

VDD + 0.3 V

0.3 × VDD V

0.4

V

–

k

–

M

–

V

Notes

1. Typical values are at 25 °C, VDD = VDD (typ). Not 100% tested.

2. The input pull-down circuit is strong (40 k) when the input voltage is below VIL and weak (1 M) when the input voltage is above VIH.

3. This parameter is guaranteed by design and is not tested.

Document Number: 001-84458 Rev. *D

Page 9 of 19

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