GLS85LS1016A-M-I-FZJE-ED102 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

GLS85LS1016A-M-I-FZJE-ED102

SATA NANDrive™

Unspecified 

GLS85LS1002A/1004A/1008B/1016B/1032B/1064B

Industrial / Commercial Temp SATA NANDrive™

1.0 GENERAL DESCRIPTION

Fact Sheet 03.001

May 2014

Each SATA NANDrive contains an integrated SATA NAND flash memory controller and up to eight discrete

NAND flash die in a BGA package. Refer to Figure 2-1 for the SATA NANDrive block diagram.

1.1 Optimized SATA NANDrive

The heart of SATA NANDrive is the SATA NAND flash

memory controller which translates standard SATA

signals into flash media data and control signals. The

following components contribute to SATA NANDrive’s

operation.

1.1.1 Microcontroller Unit (MCU)

The MCU translates SATA commands into data and

control signals required for flash media operation.

1.1.2 Internal Direct Memory Access (DMA)

SATA NANDrive uses internal DMA allowing instant

data transfer from/to buffer to/from flash media. This

implementation eliminates microcontroller overhead

associated with the traditional, firmware-based

approach, thereby increasing the data transfer rate.

1.1.3 Power Management Unit (PMU)

The PMU controls the power consumption of SATA

NANDrive. The PMU dramatically reduces the power

consumption of SATA NANDrive by putting the part of

the circuitry that is not in operation into sleep mode. 3)

The Flash File System handles inadvertent power

interrupts and has auto-recovery capability to ensure

SATA NANDrive firmware integrity. For regular power

management, the host must send a

STANDBY_IMMEDIATE (E0h), IDLE_IMMEDIATE

(E1h), STANDBY (E2h) or IDLE (E3h) command and

wait for command ready before powering down SATA

NANDrive.

3) For management of the Sleep Mode, refer to “SATA

NANDrive Application Design Guide.”

1.1.4 Embedded Flash File System

The embedded flash file system is an integral part of

SATA NANDrive. It contains MCU firmware that

performs the following tasks:

1. Translates host side signals into flash media

writes and reads

2. Provides flash media wear leveling to spread the

flash writes across all memory address space to

increase the longevity of flash media

3. Keeps track of data file structures

4. Manages system security for the selected

protection zones

1.1.5 Error Correction Code (ECC)

High performance is achieved through optimized

hardware error detection and correction.

1.1.6 Serial Communication Interface (SCI)

The Serial Communication Interface (SCI) is designed

for error reporting. During the product development

stage, it is recommended to provide the SCI port on

the PCB to aid in design validation.

1.1.7 Multi-tasking Interface

The multi-tasking interface enables fast, sequential

write performance by allowing concurrent Read,

Program and Erase operations to multiple flash media.

1.2 SMT Reflow Consideration

The SATA NANDrive family utilizes standard NAND

flash for data storage. Because the high temperature

in a surface-mount soldering reflow process may alter

the content on NAND flash, it is recommended to

program SATA NANDrive after the reflow process.

1.3 Advanced NAND Management

SATA NANDrive’s integrated controller uses

advanced wear-leveling algorithms to substantially

increase the longevity of NAND flash media. Wear

caused by data writes is evenly distributed in all or

select blocks in the device that prevents “hot spots” in

locations that are programmed and erased extensively.

This effective wear-leveling technique results in

optimized device endurance, enhanced data retention

and higher reliability required by long-life applications.

These specifications are subject to change without notice.

© 2014 Greenliant Systems

2

05/09/2014

S71430-F

Share Link: