General
Table 9. Power consumption operating behaviors (continued)
Symbol Description
• at 25 °C
IDD_VLPR
Very-low-power run mode current—2 MHz
LIRC mode, While(1) loop in SRAM all
peripheral clock disable, 125 kHz core / 31.25
kHz flash, VDD = 3.0 V
• at 25 °C
IDD_VLPR
Very-low-power run mode current—2 MHz
LIRC mode, While(1) loop in SRAM all
peripheral clock enable, 2 MHz core / 0.5 MHz
flash, VDD = 3.0 V
• at 25 °C
IDD_WAIT
Wait mode current—core disabled, 48 MHz
system/24 MHz bus, flash disabled (flash doze
enabled), all peripheral clocks disabled,
MCG_Lite under HIRC mode, VDD = 3.0 V
IDD_WAIT
Wait mode current—core disabled, 24 MHz
system/12 MHz bus, flash disabled (flash doze
enabled), all peripheral clocks disabled,
MCG_Lite under HIRC mode, VDD = 3.0 V
IDD_VLPW Very-low-power run wait current, core disabled,
4 MHz system/ 1 MHz bus and flash, all
peripheral clocks disabled, VDD = 3.0 V
IDD_VLPW Very-low-power run wait current, core disabled,
2 MHz system/ 0.5 MHz bus and flash, all
peripheral clocks disabled, VDD = 3.0 V
IDD_VLPW Very-low-power run wait current, core disabled,
125 kHz system/ 31.25 kHz bus and flash, all
peripheral clocks disabled, VDD = 3.0 V
IDD_PSTOP2 Partial Stop 2, core and system clock disabled,
12 MHz bus and flash, VDD = 3.0 V
Min.
—
—
—
—
—
—
—
Typ.
Max.1
Unit
50
131
μA
208
289
μA
1.81
2.12
mA
1.22
1.84
mA
172
222
μA
69
105
μA
36
76
μA
—
IDD_PSTOP2 Partial Stop 2, core and system clock disabled,
flash doze enabled, 12 MHz bus, VDD = 3.0 V
1.81
2.06
mA
—
1.00
1.25
mA
IDD_STOP Stop mode current at 3.0 V
• at 25 °C and below
• at 50 °C
• at 85 °C
• at 105 °C
—
161.93 181.50
—
181.45 206.95
—
236.29 315.62
μA
—
390.33 525.63
IDD_VLPS Very-low-power stop mode current at 3.0 V
• at 25 °C and below
• at 50 °C
—
3.31
6.32
—
10.43
26.39
—
34.14
94.52
μA
Table continues on the next page...
Notes
—
—
12
Freescale Semiconductor, Inc.
Kinetis KL27 With Up To 256 KB Flash, Rev3, 08/2014.