STM32F031C4Y6 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STM32F031C4Y6

ARM®-based 32-bit MCU with up to 32 Kbyte Flash, 9 timers, ADC and communication interfaces, 2.0 - 3.6 V

STMicroelectronics 

Functional overview

STM32F031x4 STM32F031x6

3.4

Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit

data word and a CRC-32 (Ethernet) polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of

the software during runtime, to be compared with a reference signature generated at link-

time and stored at a given memory location.

3.5

3.5.1

3.5.2

3.5.3

Power management

Power supply schemes

• VDD = VDDIO1 = 2.0 to 3.6 V: external power supply for I/Os (VDDIO1) and the internal

regulator. It is provided externally through VDD pins.

• VDDA = from VDD to 3.6 V: external analog power supply for ADC, Reset blocks, RCs

and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). It is

provided externally through VDDA pin. The VDDA voltage level must be always greater

or equal to the VDD voltage level and must be established first.

• VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and

backup registers (through power switch) when VDD is not present.

For more details on how to connect power pins, refer to Figure 12: Power supply scheme.

Power supply supervisors

The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.

They are always active, and ensure proper operation above a threshold of 2 V. The device

remains in reset mode when the monitored supply voltage is below a specified threshold,

VPOR/PDR, without the need for an external reset circuit.

• The POR monitors only the VDD supply voltage. During the startup phase it is required

that VDDA should arrive first and be greater than or equal to VDD.

• The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power

supply supervisor can be disabled (by programming a dedicated Option bit) to reduce

the power consumption if the application design ensures that VDDA is higher than or

equal to VDD.

The device features an embedded programmable voltage detector (PVD) that monitors the

VDD power supply and compares it to the VPVD threshold. An interrupt can be generated

when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD

threshold. The interrupt service routine can then generate a warning message and/or put

the MCU into a safe state. The PVD is enabled by software.

Voltage regulator

The regulator has two operating modes and it is always enabled after reset.

• Main (MR) is used in normal operating mode (Run).

• Low power (LPR) can be used in Stop mode where the power demand is reduced.

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DocID025743 Rev 6

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