IS43TR16256A(2012) View Datasheet(PDF) - Integrated Silicon Solution
Part Name
Description
Manufacturer
IS43TR16256A Datasheet PDF : 81 Pages
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IS43/46TR16256A, IS43/46TR16256AL,
IS43/46TR85120A, IS43/46TR85120AL
MPR Register Address Definition
The following Table provides an overview of the available data locations, how they are addressed by MR3 A[1:0] during a
MRS to MR3, and how their individual bits are mapped into the burst order bits during a Multi Purpose Register Read.
MPR MR3 Register Definition
MR3 MR3
A[2] A[1:0]
Function
Burst
Length
Read Address
A[2:0]
Burst Order and Data Pattern
BL8
000b
Burst order 0,1,2,3,4,5,6,7
Pre-defined Data Pattern [0,1,0,1,0,1,0,1]
1b
00b
Read predefined pattern
for system Calibration
BC4
000b
Burst order 0,1,2,3
Pre-defined Data Pattern [0,1,0,1]
BC4
100b
Burst order 4,5,6,7
Pre-defined Data Pattern [0,1,0,1]
BL8
000b
Burst order 0,1,2,3,4,5,6,7
1b
01b
RFU
BC4
000b
Burst order 0,1,2,3
BC4
100b
Burst order 4,5,6,7
BL8
000b
Burst order 0,1,2,3,4,5,6,7
1b
10b
RFU
BC4
000b
Burst order 0,1,2,3
BC4
100b
Burst order 4,5,6,7
BL8
000b
Burst order 0,1,2,3,4,5,6,7
1b
11b
RFU
BC4
000b
Burst order 0,1,2,3
BC4
100b
Burst order 4,5,6,7
NOTE: Burst order bit 0 is assigned to LSB and the burst order bit 7 is assigned to MSB of the selected MPR agent
MPR Functional Description
• One bit wide logical interface via all DQ pins during READ operation.
• Register Read on x16:
o DQL[0] and DQU[0] drive information from MPR.
o DQL[7:1] and DQU[7:1] either drive the same information as DQL[0], or they drive 0b.
• Addressing during for Multi Purpose Register reads for all MPR agents:
o BA[2:0]: don’t care
o A[1:0]: A[1:0] must be equal to ‘00’b. Data read burst order in nibble is fixed
o A[2]: For BL=8, A[2] must be equal to 0b, burst order is fixed to [0,1,2,3,4,5,6,7], *) For Burst Chop 4
cases, the burst order is switched on nibble base A[2]=0b, Burst order: 0,1,2,3 *) A[2]=1b, Burst order:
4,5,6,7 *)
o A[9:3]: don’t care
o A10/AP: don’t care
o A12/BC: Selects burst chop mode on-the-fly, if enabled within MR0.
o A11, A13, A14, A15: don’t care
• Regular interface functionality during register reads:
o Support two Burst Ordering which are switched with A2 and A[1:0]=00b.
o Support of read burst chop (MRS and on-the-fly via A12/BC)
o All other address bits (remaining column address bits including A10, all bank address bits) will be ignored
by the DDR3 SDRAM.
o Regular read latencies and AC timings apply.
o DLL must be locked prior to MPR Reads.
NOTE: *) Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.
NOTE: Good reference for the example of MPR feature is the JEDEC standard No.93-3D, 4.10.4 Protocol example.
Integrated Silicon Solution, Inc. – www.issi.com –
18
Rev. 00A
11/14/2012
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