IS43TR16256A-15HBL(2012) View Datasheet(PDF) - Integrated Silicon Solution
Part Name
Description
Manufacturer
IS43TR16256A-15HBL Datasheet PDF : 81 Pages
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IS43/46TR16256A, IS43/46TR16256AL,
IS43/46TR85120A, IS43/46TR85120AL
T0
T1
CK#
Source
CK
T2
T3
T4
T5
T6
T7
diff_DQS
Tn
T0
T1
T2
T3
T4
T5
T6
CK#
Destination
CK
diff_DQS
DQ
0 or 1
0
diff_DQS
Push DQS to capture
0-1 transition
0
0
DQ
0 or 1
1
1
1
Figure 2.4.7 Write Leveling Concept
DQS - DQS# driven by the controller during leveling mode must be terminated by the DRAM based on ranks populated.
Similarly, the DQ bus driven by the DRAM must also be terminated at the controller.
One or more data bits should carry the leveling feedback to the controller across the DRAM configurations X8 and X16.
On a X16 device, both byte lanes should be leveled independently.
Therefore, a separate feedback mechanism should be available for each byte lane. The upper data bits should provide
the feedback of the upper diff_DQS(diff_UDQS) to clock relationship whereas the lower data bits would indicate the lower
diff_DQS(diff_LDQS) to clock relationship.
2.4.7.1 DRAM setting for write leveling & DRAM termination function in that mode
DRAM enters into Write leveling mode if A7 in MR1 set ’High’ and after finishing leveling, DRAM exits from write leveling
mode if A7 in MR1 set ’Low’. Note that in write leveling mode, only DQS/DQS# terminations are activated and deactivated
via ODT pin, unlike normal operation.
MR setting involved in the leveling procedure
Function
Write leveling enable
Output buffer mode (Qoff)
MR1
A7
A12
Enable
1
0
Disable
0
1
DRAM termination function in the leveling mode
ODT pin @DRAM
DQS/DQS# termination
DQs termination
De-asserted
Off
Off
Asserted
On
Off
NOTE: In Write Leveling Mode with its output buffer disabled (MR1[bit7] = 1 with MR1[bit12] = 1) all RTT_Nom settings are allowed; in Write Leveling
Mode with its output buffer enabled (MR1[bit7] = 1 with MR1[bit12] = 0) only RTT_Nom settings of RZQ/2, RZQ/4 and RZQ/6 are allowed.
Integrated Silicon Solution, Inc. – www.issi.com –
25
Rev. 00A
11/14/2012
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