IS43TR16256A-15HBLI(2012) View Datasheet(PDF) - Integrated Silicon Solution
Part Name
Description
Manufacturer
IS43TR16256A-15HBLI Datasheet PDF : 81 Pages
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IS43/46TR16256A, IS43/46TR16256AL,
IS43/46TR85120A, IS43/46TR85120AL
2.4.7.2 Procedure Description
The Memory controller initiates Leveling mode of all DRAMs by setting bit 7 of MR1 to 1. When entering write leveling mode, the
DQ pins are in undefined driving mode. During write leveling mode, only NOP or DESELECT commands are allowed, as well as
an MRS command to exit write leveling mode. Since the controller levels one rank at a time, the output of other ranks must be
disabled by setting MR1 bit A12 to 1.
The Controller may assert ODT after tMOD, at which time the DRAM is ready to accept the ODT signal.
The Controller may drive DQS low and DQS# high after a delay of tWLDQSEN, at which time the DRAM has applied on-die
termination on these signals. After tDQSL and tWLMRD, the controller provides a single DQS, DQS# edge which is used by the
DRAM to sample CK - CK# driven from controller. tWLMRD(max) timing is controller dependent.
DRAM samples CK - CK# status with rising edge of DQS - DQS# and provides feedback on all the DQ bits asynchronously after
tWLO timing. Either one or all data bits ("prime DQ bit(s)") provide the leveling feedback. The DRAM's remaining DQ bits are
driven Low statically after the first sampling procedure. There is a DQ output uncertainty of tWLOE defined to allow mismatch on
DQ bits. The tWLOE period is defined from the transition of the earliest DQ bit to the corresponding transition of the latest DQ
bit. There are no read strobes (DQS/DQS#) needed for these DQs. Controller samples incoming DQ and decides to increment
or decrement DQS - DQS# delay setting and launches the next DQS/DQS# pulse after some time, which is controller
dependent. Once a 0 to 1 transition is detected, the controller locks DQS - DQS# delay setting and write leveling is achieved for
the device. Figure 2.4.7.2 describes the timing diagram and parameters for the overall Write Leveling procedure.
CK#(5)
CK
CMD
(2)
MRS
ODT
diff_DQS(4)
(3)
NOP
NOP
tMOD
tWLDQSEN
NOP
tWLS
T1
tWLH
NOP
NOP
NOP
tDQSL(6)
tDQSH(6)
tWLS
T2
tWLH
NOP
NOP
NOP
NOP
tDQSL(6)
tDQSH(6)
NOP
One Prime DQ:
Prime DQ(1)
Late Remaining DQs
Early Remaining DQs
All DQs are Prime:
Late Remaining DQs(1)
Early Remaining DQs(1)
tWLMRD
tWLMRD
tWLO
tWLO
tWLO
tWLO
tWLOE
tWLO
tWLOE
tWLO
tWLO
tWLO
Undefined
Driving Mode
Time Break DON’T CARE
Notes:
1. DRAM has the option to drive leveling feedback on a prime DQ or all DQs. If feedback is driven only on one DQ, the remaining DQs must be driven
low, as shown in above Figure, and maintained at this state throughout the leveling procedure.
2. MRS: Load MR1 to enter write leveling mode.
3. NOP: NOP or Deselect.
4. diff_DQS is the differential data strobe (DQS, DQS#). Timing reference points are the zero crossings. DQS is shown with solid line, DQS# is shown
with dotted line.
5. CK, CK# : CK is shown with solid dark line, where as CK# is drawn with dotted line.
6. DQS, DQS# needs to fulfill minimum pulse width requirements tDQSH(min) and tDQSL(min) as defined for regular Writes; the max pulse width is
system dependent.
Figure 2.4.7.2 Write leveling sequence [DQS - DQS# is capturing CK-CK# low at T1 and CK-CK# high at T2]
Integrated Silicon Solution, Inc. – www.issi.com –
26
Rev. 00A
11/14/2012
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