IS43TR16256A-125KBL(2012) View Datasheet(PDF) - Integrated Silicon Solution
Part Name
Description
Manufacturer
IS43TR16256A-125KBL Datasheet PDF : 81 Pages
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IS43/46TR16256A, IS43/46TR16256AL,
IS43/46TR85120A, IS43/46TR85120AL
4. AC & DC INPUT MEASUREMENT LEVELS
4.1. AC and DC Logic Input Levels for Single-Ended Signals
4.1.1 AC and DC Input Levels for Single-Ended Command and Address Signals
Symbol
Parameter
DDR3-800/1066/1333/1600
Min
Max
Unit
VIH.DQ(DC100)
DC input logic high
Vref + 0.100
VDD
V
VIL.DQ(DC100)
DC input logic low
VSS
Vref - 0.100
V
VIH.DQ(AC175)
AC input logic high
Vref + 0.175
Note 2
V
VIL.DQ(AC175)
AC input logic low
Note 2
Vref - 0.175
V
VIH.CA(AC150)
AC input logic high
Vref + 0.150
Note2
V
VIL.CA(AC150)
AC input logic low
Note2
Vref - 0.150
V
VREFCA(DC)
Reference Voltage for ADD, CMD inputs
0.49 * VDD
0.51 * VDD
V
Note
1
1
1,2
1,2
1,2
1,2
3,4
Symbol
Parameter
DDR3L-800/1066/1333/1600
Min
Max
Unit
Note
VIH.DQ(DC90)
DC input logic high
Vref + 0.09
VDD
V
1
VIL.DQ(DC90)
DC input logic low
VSS
Vref - 0.09
V
1
VIH.DQ(AC160)
AC input logic high
Vref + 0.160
Note 2
V
1,2
VIL.DQ(AC160)
AC input logic low
Note 2
Vref - 0.160
V
1,2
VIH.CA(AC135)
AC input logic high
Vref + 0.135
Note2
V
1,2
VIL.CA(AC135)
AC input logic low
Note2
Vref - 0.135
V
1,2
VREFCA(DC)
Reference Voltage for ADD, CMD inputs
0.49 * VDD
0.51 * VDD
V
3,4
Notes:
1. For input only pins except RESET.Vref=VrefCA(DC)
2. See "Overshoot and Undershoot Specifications"
3. The ac peak noise on Vref may not allow Vref to deviate from Vref(DC) by more than +/- 0.1% VDD.
4. For reference: DDR3 has approx. VDD/2 +/- 15mV, DDR3L has approx VDD/2 +/- 13.5mV.
5. To allow VREFCA margining, all DRAM Command and Address Input Buffers MUST use external VREF (provided by system) as the input for their
VREFCA pins. All VIH/L input level MUST be compared with the external VREF level at the 1st stage of the Command and Address input buffer
4.1.2 AC and DC Logic Input Levels for Single-Ended Signals & DQ and DM
Symbol
Parameter
VIH.DQ(DC100) DC input logic high
VIL.DQ(DC100) DC input logic low
VIH.DQ(AC175) AC input logic high
VIL.DQ(AC175) AC input logic low
VIH.DQ(AC150) AC input logic high
VIL.DQ(AC150)
VREFDQ(DC)
VREFDQ_t(DC)
AC input logic low
Reference Voltage for
DQ, DM inputs
Reference Voltage for
trained DQ, DM inputs
DDR3-800/1066
Min.
Max.
DDR3-1333/1600
Min.
Max.
DDR3-1866
Unit
Min.
Max.
Vref
+0.100
VDD
Vref
+0.100
VDD
Vref
+0.100
VDD
V
VSS
Vref -
0.100
VSS
Vref -
0.100
VSS
Vref -
0.100
V
Vref
+0.175
Note2
-
-
-
-
V
Note2
Vref -
0.175
-
-
-
-
V
Vref
+0.150
Note2
Vref
+0.150
Note2
-
-
V
Note2
Vref -
0.150
Note2
Vref -
0.150
-
-
V
0.49
*VDD
0.51 *VDD
0.49
*VDD
0.51 *VDD 0.49 *VDD
0.51
*VDD
V
0.45
*VDD
0.55 *VDD
0.45
*VDD
0.55 *VDD 0.45 *VDD
0.55
*VDD
V
Note
1
1
1,2,5
1,2,5
1,2,5
1,2,5
3,4
3,4,
6,7
Integrated Silicon Solution, Inc. – www.issi.com –
30
Rev. 00A
11/14/2012
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