IS43TR16256A(2012) View Datasheet(PDF) - Integrated Silicon Solution
Part Name
Description
Manufacturer
IS43TR16256A Datasheet PDF : 81 Pages
| |||
IS43/46TR16256A, IS43/46TR16256AL,
IS43/46TR85120A, IS43/46TR85120AL
Clock Timing
Minimum Clock Cycle Time (DLL off mode)
Average Clock Period
Average high pulse width
Average low pulse width
Absolute Clock Period
Absolute clock HIGH pulse width
Absolute clock LOW pulse width
Clock Period Jitter
Clock Period Jitter during DLL locking period
Cycle to Cycle Period Jitter
Cycle to Cycle Period Jitter during DLL
locking period
Duty Cycle Jitter
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Cumulative error across 12 cycles
Cumulative error across n = 13, 14 . . . 49, 50
cycles
Data Timing
DQS, DQS# to DQ skew, per group, per
access
DQ output hold time from DQS, DQS#
DQ low-impedance time from CK, CK#
DQ high impedance time from CK, CK#
Data setup time to DQS, DQS# referenced to
Vih(ac) / Vil(ac) levels
Data setup time to DQS, DQS# referenced to
Vih(ac) / Vil(ac) levels
Data hold time from DQS, DQS# referenced
to Vih(dc) / Vil(dc) levels
DQ and DM Input pulse width for each input
Data Strobe Timing
DQS,DQS# differential READ Preamble
tCK(DLL_OFF)
tCK(avg)
tCH(avg)
tCL(avg)
tCK(abs)
tCH(abs)
tCL(abs)
JIT(per)
JIT(per, lck)
tJIT(cc)
JIT(cc, lck)
tJIT(duty)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6per)
tERR(7per)
tERR(8per)
tERR(9per)
tERR(10per)
tERR(11per)
tERR(12per)
tERR(nper)
tDQSQ
tQH
tLZ(DQ)
tHZ(DQ)
tDS(base)
AC175
tDS(base)
AC150
tDH(base)
DC100
tDIPW
tRPRE
DQS, DQS# differential READ Postamble
tRPST
DQS, DQS# differential output high time
DQS, DQS# differential output low time
DQS, DQS# differential WRITE Preamble
DQS, DQS# differential WRITE Postamble
DQS, DQS# rising edge output access time
from rising CK, CK#
tQSH
tQSL
tWPRE
tWPST
tDQSCK
Parameter
Symbol
DQS and DQS# low-impedance time
tLZ(DQS)
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
Min.
Max.
Min.
Max.
8
-
8
-
Refer to Standard Speed Bins
0.47
0.53
0.47
0.53
0.47
0.53
0.47
0.53
Min.: tCK(avg)min + tJIT(per)min
Max.: tCK(avg)max + tJIT(per)max
0.43
-
0.43
-
0.43
-
0.43
-
-80
80
-70
70
-70
70
-60
60
160
160
140
140
140
140
120
120
-
-
-
-
-118
118
-103
103
-140
140
-122
122
-155
155
-136
136
-168
168
-147
147
-177
177
-155
155
-186
186
-163
163
-193
193
-169
169
-200
200
-175
175
-205
205
-180
180
-210
210
-184
184
-215
215
-188
188
tERR(nper)min = (1 + 0.68ln(n)) * tJIT(per)min
tERR(nper)max = (1 + 0.68ln(n)) *
tJIT(per)max
-
125
-
100
0.38
-
0.38
-
-500
250
-450
225
-
250
-
225
See table for Data Setup and Hold
400
-
360
-
0.9
Note 19
0.3
Note 11
0.4
-
0.4
-
0.9
-
0.3
-
-255
255
DDR3/DDR3L-1333
Min.
Max.
-500
250
0.9
Note
19
0.3
Note
11
0.4
-
0.4
-
0.9
-
0.3
-
-225
225
DDR3/DDR3L-1600
Min.
Max.
-450
225
ns
6
ps
tCK(avg)
tCK(avg)
ps
tCK(avg)
25
tCK(avg)
26
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
tCK(avg)
ps
ps
ps
ps
ps
ps
13
13,g
13,14,f
13,14,f
d,17
d,17
d,17
28
Note
13,19,g
Note
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
Units
11,13,g
13,g
13,g
13,f
Notes
tCK(avg) 13,14,f
61
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