IS43TR16256AL View Datasheet(PDF) - Integrated Silicon Solution

Part Name

Description

Manufacturer

IS43TR16256AL

512Mx8, 256Mx16 4Gb DDR3 SDRAM

Integrated Silicon Solution 

IS43/46TR16256A, IS43/46TR16256AL,

IS43/46TR85120A, IS43/46TR85120AL

Specific Note f

When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper), act of

the input clock, where 2 <= m <=12. (output derating are relative to the SDRAM input clock.)

For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = -172ps and tERR(mper),act,max

= 193ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = -400ps - 193ps = -593ps and

tDQSCK,max(derated) = tDQSCK,max - ERR(mper),act,min = 400ps + 172ps = 572ps. Similarly, tLZ(DQ) for DDR3-800

derates to tLZ(DQ),min(derated) = -800ps - 193ps = -993ps and tLZ(DQ),max(derated) = 400ps + 172ps = 572ps.

(Caution on the min/max usage!)

Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <= 12, and

tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12.

Specific Note g

When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the

input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800

SDRAM has tCK(avg),act=2500ps, tJIT(per),act,min = -72ps and tJIT(per),act,max = 93ps, then tRPRE,min(derated) =

tRPRE,min + tJIT(per),act,min = 0.9 x tCK(avg),act + tJIT(per),act,min = 0.9 x 2500ps - 72ps = 2178ps. Similarly,

tQH,min(derated) = tQH,min + tJIT(per),act,min = 0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x 2500ps - 72ps = 878ps.

(Caution on the min/max usage!)

9.4.2 Timing Parameters

1. Actual value dependent upon measurement level definitions.

2. Commands requiring a locked DLL are: READ ( and RAP) are synchronous ODT commands.

3. The max values are system dependent.

4. WR as programmed in mode register.

5. Value must be rouned-up to next higher integer value.

6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.

7. For definition of RTT-on time tAON See “Timing Parameters”.

8. For definition of RTT-off time tAOF See “Timing Parameters”.

9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.

10. WR in clock cycles are programmed in MR0.

11. The maximum read postamble is bonded by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the

right side.

12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this

parameter needs to be derated by TBD.

13. Value is only valid for RON34.

14. Single ended signal parameter.

15. tREFI depends on TOPER.

16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew

rate. Note for DQ and DM signals, VREF(DC)=VRefDQ(DC). For input only pins except RESET,

VRef(DC)=VRefCA(DC).

17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate.

18. Note for DQ and DM signals, VREF(DC)=VRefDQ(DC). For input only pins except RESET, VRef(DC)=VRefCA(DC).

19. Start of internal write transaction is defined as follows:

20. For BL8 (fixed by MRS and on-the-fly): Rising clock edge 4 clock cycles after WL.

21. For BC4 (on-the-fly): Rising clock edge 4 clock cycles after WL.

22. For BC4 (fixed by MRS): Rising clock edge 2 clock cycles after WL.

19. The maximum preamble is bound by tLZ(DQS)max on the left side and tDQSCK(max) on the right side.

20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are

in progress, but power-down IDD spec will not be applied until finishing those operations.

21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there

are cases where additional time such as tXPDLL(min) is also required.

22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.

Integrated Silicon Solution, Inc. – www.issi.com –

71

Rev. I

04/27/2017

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