PIC18F65J50-I/PT View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F65J50-I/PT

64/80-Pin High-Performance, 1-Mbit Flash USB Microcontrollers with nanoWatt Technology

Microchip Technology 

PIC18F87J50 FAMILY

TABLE 1-3: PIC18F6XJ5X PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number Pin Buffer

64-TQFP Type Type

Description

MCLR

7

I

ST Master Clear (Reset) input. This pin is an active-low Reset

to the device.

OSC1/CLKI/RA7

OSC1

CLKI

RA7(3)

39

Oscillator crystal or external clock input.

I

ST

Oscillator crystal input or external clock source input.

ST buffer when configured in RC mode; CMOS

otherwise.

I CMOS Main oscillator input connection.

External clock source input. Always associated

with pin function OSC1. (See related OSC1/CLKI,

OSC2/CLKO pins.)

I/O TTL Main clock input connection.

General purpose I/O pin.

OSC2/CLKO/RA6

OSC2

CLKO

RA6(3)

40

Oscillator crystal or clock output.

O

—

Oscillator crystal output. Connects to crystal or

resonator in Crystal Oscillator mode.

O

— Main oscillator feedback output connection.

In RC mode, OSC2 pin outputs CLKO which has

1/4 the frequency of OSC1 and denotes the

instruction cycle rate.

I/O TTL System cycle clock output (FOSC/4).

General purpose I/O pin.

Legend:

Note 1:

2:

3:

TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

Analog = Analog input

I = Input

O

= Output

P = Power

OD

= Open-Drain (no P diode to VDD)

Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.

Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared.

RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.

DS39775B-page 12

Preliminary

© 2007 Microchip Technology Inc.

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