PIC18F65J50T View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F65J50T

64/80-Pin High-Performance, 1-Mbit Flash USB Microcontrollers with nanoWatt Technology

Microchip Technology 

Pin Diagrams (Continued)

80-Pin TQFP

PIC18F87J50 FAMILY

RH2/A18/PMD7(4)

1

RH3/A19/PMD6(4)

2

RE1/AD9/PMWR(3)/P2C

3

RE0/AD8/PMRD(3)/P2D

4

RG0/PMA8/ECCP3/P3A

5

RG1/PMA7/TX2/CK2

6

RG2/PMA6/RX2/DT2

7

RG3/PMCS1/CCP4/P3D

8

MCLR

9

RG4/PMCS2/CCP5/P1D

10

VSS

11

VDDCORE/VCAP

12

RF7/PMD0(4)/SS1/C1OUT

13

RF6/PMD1(4)/AN11/C1INA

14

RF5/PMD2(4)/AN10/

C1INB/CVREF

15

RF4/D+

16

RF3/D-

17

RF2/PMA5/AN7/C2INB

18

RH7/PMWR(4)/AN15/P1B(2)

19

RH6/PMRD(4)/AN14/

20

P1C(2)/C1INC

PIC18F8XJ5X

60

RJ2/WRL

59

RJ3/WRH

58

RB0/FLT0/INT0

57

RB1/INT1/PMA4

56

55

RB2/INT2/PMA3

RB3/INT3/ECCP2(1)/

P2A(1)/PMA2

54

RB4/KBI0/PMA1

53

RB5/KBI1/PMA0

52

RB6/KBI2/PGC

51

VSS

50

OSC2/CLKO/RA6

49

OSC1/CLKI/RA7

48

VDD

47

RB7/KBI3/PGD

46

RC5/SDO1/C2OUT

45

RC4/SDI1/SDA1

44

RC3/SCK1/SCL1

43

RC2/ECCP1/P1A

42

RJ7/UB

41

RJ6/LB

Note 1:

2:

3:

4:

The ECCP2/P2A pin placement depends on the setting of the CCP2MX Configuration bit and the program memory mode.

P1B, P1C, P3B and P3C pin placement depends on the setting of the ECCPMX Configuration bit.

PMP pin placement when PMPMX = 1.

PMP pin placement when PMPMX = 0.

© 2007 Microchip Technology Inc.

Preliminary

DS39775B-page 3

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