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PIC18F65J50_09 View Datasheet(PDF) - Microchip Technology

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PIC18F65J50_09 Datasheet PDF : 16 Pages
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PIC18F87J50 FAMILY
2. Module: Table 28-2: Comparator
Specifications
On page 431, the maximum Input Offset Voltage
(parameter D300) is changed to ±25 mV.
The parameter numbers for TRESP and TMC2OV
are changed to D303 and D304, respectively.
A new parameter number, D305, for VIRV is added.
The changed/appended content is indicated in
bold text in Table 28-2.
3. Module: Table 28-4: Internal Voltage
Regulator Specifications
On page 431, additional comments are provided to
help guide selection of an external capacitor.
The changed/appended content is indicated in
bold text in Table 28-4.
TABLE 28-2: COMPARATOR SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Sym
Characteristics
Min
Typ
Max Units
Comments
D300
D301
D302
D303
D304
D305
Note 1:
VIOFF Input Offset Voltage
±5.0
±25
mV
VICM
Input Common Mode Voltage
0
— AVDD – 1.5 V
CMRR Common Mode Rejection Ratio 55
dB
TRESP Response Time(1)
150
400
ns
TMC2OV Comparator Mode Change to
10
μs
Output Valid
VIRV
Internal Reference Voltage
1.2
V
Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.
TABLE 28-4: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: -40°C < TA < +85°C (unless otherwise stated)
Param
No.
Sym
Characteristics
Min Typ Max Units
Comments
VRGOUT Regulator Output Voltage
CEFC
External Filter Capacitor
Value(1)
2.45 2.5 —
4.7(2) 10 —
V VDD, ENVREG = 3.0V
μF Capacitor must be low series
resistance (<5Ω)
Note 1: CEFC applies when the internal regulator is enabled (ENVREG = VDD). When the regulator is
disabled (ENVREG = VSS), there is no minimum or maximum capacitance, but good supply rail bypassing
should still be practiced.
2: If the regulator is enabled and the VDD supply rail has moderate ripple voltage, it is recommended that
more than the minimum CEFC be used.
DS80481A-page 6
© 2009 Microchip Technology Inc.

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