TDA7550R_01 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

TDA7550R_01

DIGITAL SIGNAL PROCESSING IC FOR SPEECH AND AUDIO APPLICATIONS

STMicroelectronics 

TDA7550R

– Two Read Offset Register

PLL

The Euterpe clock system generates the fol-

lowing clocks:

– DCLK

the DSP core clock

– MCLK

CODEC master clock

– LRCLK

left/right clock for the SAI and

the CODEC

– SCLK

shift serial clock for the SAI and

the CODEC

The output of the PLL operates from 70 to 140

MHz. The DSP core can operate with a clock

up to 48.2 MHz.

The audio clock are derived from the VCO out-

put.

CODEC CELL

The main features of the CODEC cell are listed

below:

– one 16-bit Delta Sigma Stereo ADC

– 80 dB Dynamic Range

– Oversampling Ratio: 128

– one 16-bit Delta Sigma Stereo DAC

– 80 dB Dynamic Range

– Interpolating Ratio: 128

– Sampling rates of 4kHz to 48kHz

– Signal Noise Ratio: 80 dB Typ.

The analog interface is in the form of differen-

tial signals for each channel. The interface on

the digital side has the form of an SAI interface

and can interface directly to an SAI channel

and then to the DSP core.

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