K6R1016C1D-E(2001) View Datasheet(PDF) - Samsung
Part Name
Description
Manufacturer
K6R1016C1D-E Datasheet PDF : 11 Pages
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K6R1016C1D
PREPLrIeMliImNiAnaRryY
CMOS SRAM
64K x 16 Bit High-Speed CMOS Static RAM
FEATURES
• Fast Access Time 10,12(Max.)
• Power Dissipation
Standby (TTL) : 20mA(Max.)
(CMOS) : 5mA(Max.)
Operating K6R1016C1D-10 : 65mA(Max.)
K6R1016C1D-12 : 55mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Data Byte Control: LB: I/O1~ I/O8, UB: I/O9~ I/O16
• Standard Pin Configuration:
K6R1016C1D-J : 44-SOJ-400
K6R1016C1D-T: 44-TSOP2-400BF
K6R1016C1D-E: 48-TBGA ( 6.0mm X 7.0mm )
with 0.75 ball pitch
• Operating in Commercial and Industrial Temperature range.
GENERAL DESCRIPTION
The K6R1016C1D is a 1,048,576-bit high-speed Static Random
Access Memory organized as 65,536 words by 16 bits. The
K6R1016C1D uses 16 common input and output lines and has
at output enable pin which operates faster than address access
time at read cycle. Also it allows that lower and upper byte
access by data byte control (UB, LB). The device is fabricated
using SAMSUNG′s advanced CMOS process and designed for
high-speed circuit technology. It is particularly well suited for
use in high-density high-speed system applications. The
K6R1016C1D is packaged in a 400mil 44-pin plastic SOJ or
TSOP2 forward or 48-TBGA.
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
A0
A1
A2
A3
A4
A5
A6
A7
A8
I/O1~I/O8
I/O9~I/O16
Data
Cont.
Data
Cont.
Gen.
CLK
Pre-Charge Circuit
Memory Array
512 Rows
128x16 Columns
I/O Circuit &
Column Select
A9 A10 A11 A12 A13 A14 A15
WE
OE
UB
LB
CS
PIN FUNCTION
Pin Name
A0 - A15
WE
CS
OE
LB
UB
I/O1 ~ I/O16
VCC
VSS
N.C
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Lower-byte Control(I/O1~I/O8)
Upper-byte Control(I/O9~I/O16)
Data Inputs/Outputs
Power(+5.0V)
Ground
No Connection
-3-
Revision 0.3
December 2001
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