ATF22LV10CQZ-30SU_05 View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATF22LV10CQZ-30SU_05

High-performance EE PLD

Atmel Corporation 

4.4 Input Test Waveforms

4.4.1 Input Test Waveforms and Measurement Levels

4.4.2 Output Test Loads

Note:

Similar competitors devices are specified with slightly different loads. These load differences may

affect output signals’ delay and slew rate. Atmel devices are tested with sufficient margins to meet

compatible device specification conditions.

4.5 Pin Capacitance

Table 4-1. Pin Capacitance (f = 1 MHz, T = 25°C(1))

Typ

Max

Units

Conditions

CIN

CI/O

Note:

5

8

pF

VIN = 0V

6

8

pF

VOUT = 0V

1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100%

tested.

4.6 Power-up Reset

The registers in the ATF22LV10CZ/CQZ are designed to reset during power-up. At a point

delayed slightly from VCC crossing VRST, all registers will be reset to the low state. The output

state will depend on the polarity of the buffer.

This feature is critical for state machine initialization. However, due to the asynchronous nature

of reset and the uncertainty of how VCC actually rises in the system, the following conditions are

required:

1. The VCC rise must be monotonic and start below 0.7V.

2. The clock must remain stable during TPR.

3. After TPR, all input and feedback setup times must be met before driving the clock pin

high.

4.7 Preload of Register Outputs

The ATF22LV10CZ/CQZ’s registers are provided with circuitry to allow loading of each register

with either a high or a low. This feature will simplify testing since any state can be forced into the

registers to control test sequencing. A JEDEC file with preload is generated when a source file

6 ATF22LV10C(Q)Z

0779L–PLD–12/05

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