S25FL256SDSBFIQ01 View Datasheet(PDF) - Spansion Inc.

Part Name

Description

Manufacturer

S25FL256SDSBFIQ01

MirrorBit® Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O

Spansion Inc. 

Data Sheet

4. Signal Protocols

4.1 SPI Clock Modes

4.1.1

4.1.2

Single Data Rate (SDR)

The S25FL128S and S25FL256S devices can be driven by an embedded microcontroller (bus master) in

either of the two following clocking modes.

 Mode 0 with Clock Polarity (CPOL) = 0 and, Clock Phase (CPHA) = 0

 Mode 3 with CPOL = 1 and, CPHA = 1

For these two modes, input data into the device is always latched in on the rising edge of the SCK signal and

the output data is always available from the falling edge of the SCK clock signal.

The difference between the two modes is the clock polarity when the bus master is in standby mode and not

transferring any data.

 SCK will stay at logic low state with CPOL = 0, CPHA = 0

 SCK will stay at logic high state with CPOL = 1, CPHA = 1

POL=0_CPHA=0_SCLK

POL=1_CPHA=1_SCLK

CS#

SI

SO

Figure 4.1 SPI SDR Modes Supported

MSB

MSB

Timing diagrams throughout the remainder of the document are generally shown as both mode 0 and 3 by

showing SCK as both high and low at the fall of CS#. In some cases a timing diagram may show only mode 0

with SCK low at the fall of CS#. In such a case, mode 3 timing simply means clock is high at the fall of CS# so

no SCK rising edge set up or hold time to the falling edge of CS# is needed for mode 3.

SCK cycles are measured (counted) from one falling edge of SCK to the next falling edge of SCK. In mode 0

the beginning of the first SCK cycle in a command is measured from the falling edge of CS# to the first falling

edge of SCK because SCK is already low at the beginning of a command.

Double Data Rate (DDR)

Mode 0 and Mode 3 are also supported for DDR commands. In DDR commands, the instruction bits are

always latched on the rising edge of clock, the same as in SDR commands. However, the address and input

data that follow the instruction are latched on both the rising and falling edges of SCK. The first address bit is

latched on the first rising edge of SCK following the falling edge at the end of the last instruction bit. The first

bit of output data is driven on the falling edge at the end of the last access latency (dummy) cycle.

SCK cycles are measured (counted) in the same way as in SDR commands, from one falling edge of SCK to

the next falling edge of SCK. In mode 0 the beginning of the first SCK cycle in a command is measured from

the falling edge of CS# to the first falling edge of SCK because SCK is already low at the beginning of a

command.

July 12, 2012 S25FL128S_256S_00_05

S25FL128S and S25FL256S

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