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S25FL256SDSBFIQ01 View Datasheet(PDF) - Cypress Semiconductor

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S25FL256SDSBFIQ01 Datasheet PDF : 144 Pages
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S25FL128S, S25FL256S
5.3.2
Hardware (Warm) Reset
When the RESET# input transitions from VIH to VIL the device will reset register states in the same manner as power-on reset but,
does not go through the full reset process that is performed during POR. The hardware reset process requires a period of tRPH to
complete. If the POR process did not complete correctly for any reason during power-up (tPU), RESET# going low will initiate the full
POR process instead of the hardware reset process and will require tPU to complete the POR process.
The RESET# input provides a hardware method of resetting the flash memory device to standby state.
RESET# must be high for tRS following tPU or tRPH, before going low again to initiate a hardware reset.
When RESET# is driven low for at least a minimum period of time (tRP), the device terminates any operation in progress, tri-
states all outputs, and ignores all read/write commands for the duration of tRPH. The device resets the interface to standby
state.
If CS# is low at the time RESET# is asserted, CS# must return high during tRPH before it can be asserted low again after tRH.
Hardware Reset is only offered in 16-lead SOIC and BGA packages.
Figure 5.7 Hardware Reset
RESET#
CS#
Any prior reset
tRPH
tRH
tRS
tRP
tRH
tRPH
Table 5.3 Hardware Reset Parameters
Parameter
Description
Limit
Time
Unit
tRS
Reset Setup —
Prior Reset end and RESET# high before RESET# low
Min
50
ns
tRPH
tRP
tRH
Reset Pulse Hold - RESET# low to CS# low
RESET# Pulse Width
Reset Hold - RESET# high before CS# low
Min
35
µs
Min
200
ns
Min
50
ns
Notes:
1. RESET# Low is optional and ignored during Power-up (tPU). If Reset# is asserted during the end of tPU, the device will remain in the reset state and tRH will determine
when CS# may go Low.
2. Sum of tRP and tRH must be equal to or greater than tRPH.
Document Number: 001-98283 Rev. *I
Page 31 of 144

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