S25FL256SDSBFIQ01 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
S25FL256SDSBFIQ01
Cypress Semiconductor
S25FL256SDSBFIQ01 Datasheet PDF : 144 Pages
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S25FL128S, S25FL256S
1.2.2.2
Secure Silicon Region (OTP)
The size and format (address map) of the One Time Program area is different from prior generations. The method for protecting
each portion of the OTP area is different. For additional details see Secure Silicon Region (OTP) on page 57.
1.2.2.3
Configuration Register Freeze Bit
The configuration register Freeze bit CR1[0], locks the state of the Block Protection bits as in prior generations. In the FL-S family it
also locks the state of the configuration register TBPARM bit CR1[2], TBPROT bit CR1[5], and the Secure Silicon Region (OTP)
area.
1.2.2.4
Sector Erase Commands
The command for erasing an 8-kbyte area (two 4-kbyte sectors) is not supported.
The command for erasing a 4-kbyte sector is supported only in the 128-Mbit and 256-Mbit density FL-S devices and only for use on
the thirty two 4-kbyte parameter sectors at the top or bottom of the device address space.
The erase command for 64-kbyte sectors are supported for the 128-Mbit and 256-Mbit density FL-S devices when the ordering
option for 4-kbyte parameter sectors with 64-kbyte uniform sectors are used. The 64-kbyte erase command may be applied to erase
a group of sixteen 4-kbyte sectors.
The erase command for a 256-kbyte sector replaces the 64-kbyte erase command when the ordering option for 256-kbyte uniform
sectors is used for the 128-Mbit and 256-Mbit density FL-S devices.
1.2.2.5
Deep Power Down
The Deep Power Down (DPD) function is not supported in FL-S family devices.
The legacy DPD (B9h) command code is instead used to enable legacy SPI memory controllers, that can issue the former DPD
command, to access a new bank address register. The bank address register allows SPI memory controllers that do not support
more than 24 bits of address, the ability to provide higher order address bits for commands, as needed to access the larger address
space of the 256-Mbit density FL-S device. For additional information see Extended Address on page 45.
1.2.2.6
New Features
The FL-S family introduces several new features to SPI category memories:
Extended address for access to higher memory density.
AutoBoot for simpler access to boot code following power up.
Enhanced High Performance read commands using mode bits to eliminate the overhead of SIO instructions when
repeating the same type of read command.
Multiple options for initial read latency (number of dummy cycles) for faster initial access time or higher clock rate read
commands.
DDR read commands for SIO, DIO, and QIO.
Advanced Sector Protection for individually controlling the protection of each sector. This is very similar to the Advanced
Sector Protection feature found in several other Cypress parallel interface NOR memory families.
Document Number: 001-98283 Rev. *I
Page 7 of 144
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